MPC8540 datasheet(22/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

xxii

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

13.5.4.2

Maximum Amount of SDRAM Supported.......................................................... 13-91

13.5.4.3

SDRAM Machine Limitations............................................................................. 13-92

13.5.4.3.1

Analysis of Maximum Row Number Due to Bank Select

Multiplexing ................................................................................................ 13-92

13.5.4.3.2

Bank Select Signals ......................................................................................... 13-92

13.5.4.3.3

128-Mbyte SDRAM ........................................................................................ 13-92

13.5.4.3.4

256-Mbyte SDRAM ........................................................................................ 13-95

13.5.4.3.5

512-Mbyte SDRAM ........................................................................................ 13-95

13.5.4.3.6

Power-Down Mode.......................................................................................... 13-97

13.5.4.3.7

Self-Refresh ..................................................................................................... 13-97

13.5.4.3.8

SDRAM Timing .............................................................................................. 13-99

13.5.4.4

Parity Support for SDRAM ............................................................................... 13-101

13.5.5

Interfacing to ZBT SRAM ..................................................................................... 13-101

13.5.6

Interfacing to DSP Host Ports................................................................................ 13-103

13.5.6.1

Interfacing to MSC8101 HDI16 ........................................................................ 13-103

13.5.6.1.1

HDI16 Peripherals ......................................................................................... 13-103

13.5.6.1.2

Physical Interconnections .............................................................................. 13-105

13.5.6.1.3

Supporting Burst Transfers............................................................................ 13-106

13.5.6.1.4

Host 60x Bus: HDI16 Peripheral Interface Hardware Timings..................... 13-107

13.5.6.2

Interfacing to MSC8102 DSI............................................................................. 13-107

13.5.6.2.1

DSI in Asynchronous SRAM-Like Mode ..................................................... 13-108

13.5.6.2.2

DSI in Synchronous Mode ............................................................................ 13-110

13.5.6.2.3

Broadcast Accesses........................................................................................ 13-118

13.5.6.3

Interfacing to EHPI from Texas Instruments TMS320Cxxxx DSPs ................. 13-118

13.5.6.3.1

Expansion to Multiple DSPs.......................................................................... 13-121

Chapter 14

Three-Speed Ethernet Controllers

14.1

Introduction.................................................................................................................... 14-1

14.1.1

Three-Speed Ethernet Controller Overview .............................................................. 14-7

14.2

Features .......................................................................................................................... 14-7

14.3

Modes of Operation ....................................................................................................... 14-8

14.4

External Signal Descriptions ......................................................................................... 14-9

14.4.1

Detailed Signal Descriptions ................................................................................... 14-10

14.5

Memory Map/Register Definition ............................................................................... 14-13

14.5.1

Top-Level Module Memory Map ............................................................................ 14-13

14.5.2

Detailed Memory Map—Control/Status Registers.................................................. 14-14

14.5.3

Memory-Mapped Register Descriptions.................................................................. 14-20

14.5.3.1

TSEC General Control and Status Registers ....................................................... 14-20

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