MPC8540 datasheet(38/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

xxxviii

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

19.2

External Signal Descriptions ......................................................................................... 19-3

19.3

Memory Map and Register Definition........................................................................... 19-3

19.3.1

Register Summary...................................................................................................... 19-3

19.3.2

Control Registers ....................................................................................................... 19-5

19.3.2.1

Performance Monitor Global Control Register (PMGC0) .................................... 19-5

19.3.2.2

Performance Monitor Local Control Registers

(PMLCAn and PMLCBn) ................................................................................. 19-5

19.3.3

Counter Registers....................................................................................................... 19-9

19.3.3.1

Performance Monitor Counters (PMC0–PMC8)................................................... 19-9

19.4

Functional Description................................................................................................. 19-10

19.4.1

Performance Monitor Interrupt................................................................................ 19-10

19.4.2

Event Counting ........................................................................................................ 19-11

19.4.3

Threshold Events ..................................................................................................... 19-11

19.4.4

Chaining................................................................................................................... 19-12

19.4.5

Triggering ................................................................................................................ 19-12

19.4.6

Burstiness Counting................................................................................................. 19-13

19.4.7

Performance Monitor Events ................................................................................... 19-15

19.4.8

Performance Monitor Examples .............................................................................. 19-27

Chapter 20

Debug Features and Watchpoint Facility

20.1

Introduction.................................................................................................................... 20-1

20.1.1

Overview.................................................................................................................... 20-2

20.1.2

Features ...................................................................................................................... 20-3

20.1.3

Modes of Operation ................................................................................................... 20-3

20.1.3.1

Local Bus (LBC) Debug Mode.............................................................................. 20-4

20.1.3.2

DDR SDRAM Interface Debug Modes ................................................................. 20-4

20.1.3.3

PCI/PCI-X Interface Debug Modes....................................................................... 20-5

20.1.3.4

Watchpoint Monitor Modes ................................................................................... 20-5

20.1.3.5

Trace Buffer Modes ............................................................................................... 20-5

20.2

External Signal Descriptions ......................................................................................... 20-6

20.2.1

Overview.................................................................................................................... 20-6

20.2.2

Detailed Signal Descriptions ..................................................................................... 20-7

20.2.2.1

Debug Signals—Details......................................................................................... 20-7

20.2.2.2

Watchpoint Monitor Trigger Signals—Details ...................................................... 20-8

20.2.2.3

Test Signals—Details............................................................................................. 20-9

20.3

Memory Map/Register Definition ............................................................................... 20-10

20.3.1

Watchpoint Monitor Register Descriptions ............................................................. 20-11

20.3.1.1

Watchpoint Monitor Control Registers 0–1 (WMCR0, WMCR1)...................... 20-11

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