MPC8540 datasheet(99/1302 Pages) FREESCALE

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MPC8540 Overview

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

1-5

•

Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture.

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts

— Supports 4 message interrupts with 32-bit messages

— Supports connection of an external interrupt controller such as the 8259 programmable

interrupt controller

— Four global high resolution timers/counters that can generate interrupts

— Supports 22 other internal interrupt sources

— Supports fully nested interrupt delivery

— Interrupts can be routed to external pin for external processing.

— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.

— Interrupt summary registers allow fast identification of interrupt source.

•I

2C controller

— Two-wire interface

— Multiple-master support

— Master or slave I

2C mode support

— On-chip digital filtering rejects spikes on the bus

•

Boot sequencer

— Optionally loads configuration data from serial ROM at reset through the I

2C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I

2C addressing mode

— Data integrity checked with preamble signature and CRC

•

DUART

— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

•

10/100 fast Ethernet controller (FEC)

— Operates at 10 to 100 megabits per second (Mbps) as a device debug and maintenance

port

•

Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 166 MHz

— Eight chip selects support eight external slaves

— Four- and eight-beat burst transfers

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