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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 34 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 34 Page - Freescale Semiconductor, Inc |
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34 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 xxxiv Freescale Semiconductor Contents Paragraph Number Title Page Number 17.3.2.3.4 Port Error Capture Status Register (PECSR) .................................................. 17-52 17.3.2.3.5 Error Packet Capture Register 0 (EPCR0) ...................................................... 17-52 17.3.2.3.6 Error Packet Capture Register 1 (EPCR1) ...................................................... 17-53 17.3.2.3.7 EPCR1—Type 1 Packet Format ...................................................................... 17-53 17.3.2.3.8 EPCR1—Type 2 Packet Format ...................................................................... 17-54 17.3.2.3.9 EPCR1—Type 5 Packet Format ...................................................................... 17-54 17.3.2.3.10 EPCR1—Type 6 Packet Format ...................................................................... 17-55 17.3.2.3.11 EPCR1—Type 8 Request Packet Format ........................................................ 17-55 17.3.2.3.12 EPCR1—Type 8 Response Packet Format...................................................... 17-56 17.3.2.3.13 EPCR1—Type 10 Packet Format .................................................................... 17-56 17.3.2.3.14 EPCR1—Type 11 Packet Format .................................................................... 17-57 17.3.2.3.15 EPCR1—Type 13 Packet Format .................................................................... 17-58 17.3.2.3.16 Error Packet Capture Register 2 (EPCR2) ...................................................... 17-58 17.3.2.3.17 EPCR2—Type 1, 2, or 5 Packet Format.......................................................... 17-58 17.3.2.3.18 EPCR2—Type 6 Packet Format ...................................................................... 17-59 17.3.2.3.19 EPCR2—Type 8 Request Packet Format ........................................................ 17-59 17.3.2.3.20 EPCR2—Type 8 Response Packet Format...................................................... 17-60 17.3.2.3.21 EPCR2—Type 10 Packet Format .................................................................... 17-60 17.3.2.3.22 EPCR2—Type 11 or 13 Packet Format ........................................................... 17-61 17.3.2.3.23 Port Recoverable Error Detect Register (PREDR).......................................... 17-61 17.3.2.3.24 Port Error Recovery Threshold Register (PERTR) ......................................... 17-64 17.3.2.3.25 Port Retry Threshold Register (PRTR)............................................................ 17-64 17.3.3 RapidIO Message Unit Registers............................................................................. 17-65 17.3.3.1 RapidIO Outbound Message Registers................................................................ 17-65 17.3.3.1.1 Outbound Mode Register (OMR).................................................................... 17-65 17.3.3.1.2 Outbound Status Register (OSR)..................................................................... 17-67 17.3.3.1.3 Outbound Descriptor Queue Dequeue Pointer Address Register (ODQDPAR)................................................................................................ 17-68 17.3.3.1.4 Outbound Unit Source Address Register (OSAR) .......................................... 17-69 17.3.3.1.5 Outbound Destination Port Register (ODPR) ................................................. 17-70 17.3.3.1.6 Outbound Destination Attributes Register (ODATR) ..................................... 17-70 17.3.3.1.7 Outbound Double-Word Count Register (ODCR) .......................................... 17-71 17.3.3.1.8 Outbound Descriptor Queue Enqueue Pointer Address Register (ODQEPAR) ................................................................................................ 17-72 17.3.3.2 RapidIO Inbound Message Registers .................................................................. 17-72 17.3.3.2.1 Inbound Mode Register (IMR) ........................................................................ 17-72 17.3.3.2.2 Inbound Status Register (ISR) ......................................................................... 17-74 17.3.3.2.3 Inbound Frame Queue Dequeue Pointer Address Register (IFQDPAR).................................................................................................. 17-75 |
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