MPC8540 datasheet(41/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

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Contents

Paragraph

Number

Title

Page

Number

21.5.3.6.1

MAC Configuration Register 1 (MACCFG1)................................................. 21-38

21.5.3.6.2

MAC Configuration Register 2 (MACCFG2)................................................. 21-40

21.5.3.6.3

Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) ................................... 21-41

21.5.3.6.4

Half-Duplex Register (HAFDUP) ................................................................... 21-41

21.5.3.6.5

Maximum Frame Length Register (MAXFRM) ............................................. 21-42

21.5.3.6.6

Interface Status Register (IFSTAT) ................................................................. 21-43

21.5.3.6.7

Station Address Register Part 1 (MACSTNADDR1) ..................................... 21-43

21.5.3.6.8

Station Address Register Part 2 (MACSTNADDR2) ..................................... 21-44

21.5.3.7

Hash Function Registers ...................................................................................... 21-45

21.5.3.7.1

Individual Address Registers 0–7 (IADDRn) ................................................. 21-45

21.5.3.7.2

Group Address Registers 0–7 (GADDRn) ...................................................... 21-46

21.5.3.8

Attribute Registers ............................................................................................... 21-46

21.5.3.8.1

Attribute Register (ATTR)............................................................................... 21-46

21.5.3.8.2

Attribute Extract Length and Extract Index Register (ATTRELI) .................. 21-47

21.6

Functional Description................................................................................................. 21-48

21.6.1

Connecting to the Physical Interface ....................................................................... 21-48

21.6.1.1

Media-Independent Interface (MII) ..................................................................... 21-48

21.6.2

FEC Channel Operation........................................................................................... 21-49

21.6.2.1

Initialization Sequence......................................................................................... 21-50

21.6.2.1.1

Hardware Controlled Initialization .................................................................. 21-50

21.6.2.1.2

User Initialization ............................................................................................ 21-50

21.6.2.2

Soft Reset and Reconfiguring Procedure............................................................. 21-51

21.6.2.3

FEC Frame Transmission .................................................................................... 21-52

21.6.2.4

FEC Frame Reception.......................................................................................... 21-53

21.6.2.5

Frame Recognition............................................................................................... 21-54

21.6.2.5.1

Destination Address Recognition .................................................................... 21-55

21.6.2.5.2

Hash Table Algorithm...................................................................................... 21-57

21.6.2.5.3

CRC Computation Examples .......................................................................... 21-57

21.6.2.6

Flow Control........................................................................................................ 21-59

21.6.2.7

Interrupt Handling ............................................................................................... 21-59

21.6.2.8

Inter-Packet Gap Time ......................................................................................... 21-61

21.6.2.9

Internal and External Loop Back ......................................................................... 21-61

21.6.2.10

Error-Handling Procedure.................................................................................... 21-61

21.6.3

Buffer Descriptors.................................................................................................... 21-63

21.6.3.1

Transmit Data Buffer Descriptor (TxBD)............................................................ 21-65

21.6.3.2

Receive Buffer Descriptor (RxBD) ..................................................................... 21-67

21.6.4

Data Extraction to the L2 Cache.............................................................................. 21-69

21.7

Application Information .............................................................................................. 21-69

21.7.1

Interface Mode Configuration ................................................................................. 21-69

21.7.1.1

MII Interface Mode.............................................................................................. 21-70

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