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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 143 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 143 Page - Freescale Semiconductor, Inc |
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143 / 1302 page  Complete CCSR Map MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 2-25 0x2_0E00 L2ERRINJHI—L2 error injection mask high register R/W 0x0000_0000 7.3.1.5.1/7-13 0x2_0E04 L2ERRINJLO—L2 error injection mask low register R/W 0x0000_0000 7.3.1.5.1/7-13 0x2_0E08 L2ERRINJCTL—L2 error injection tag/ECC control register R/W 0x0000_0000 7.3.1.5.1/7-13 0x2_0E20 L2CAPTDATAHI—L2 error data high capture register R 0x0000_0000 7.3.1.5.2/7-15 0x2_0E24 L2CAPTDATALO—L2 error data low capture register R 0x0000_0000 7.3.1.5.2/7-15 0x2_0E28 L2CAPTECC—L2 error syndrome register R 0x0000_0000 7.3.1.5.2/7-15 0x2_0E40 L2ERRDET—L2 error detect register Special 0x0000_0000 7.3.1.5.2/7-15 0x2_0E44 L2ERRDIS—L2 error disable register R/W 0x0000_0000 7.3.1.5.2/7-15 0x2_0E48 L2ERRINTEN—L2 error interrupt enable register R/W 0x0000_0000 7.3.1.5.2/7-15 0x2_0E4C L2ERRATTR—L2 error attributes capture register R/W 0x0000_0000 7.3.1.5.2/7-15 0x2_0E50 L2ERRADDR—L2 error address capture register R 0x0000_0000 7.3.1.5.2/7-15 0x2_0E58 L2ERRCTL—L2 error control register R/W 0x0000_0000 7.3.1.5.2/7-15 DMA Registers General Registers 0x2_1100 MRn—DMA 0 mode register R/W 0x0000_0000 15.3.2.1/15-10 0x2_1104 SRn—DMA 0 status register Special 0x0000_0000 15.3.2.2/15-13 0x2_1108 Reserved — — — 0x2_110C CLNDARn—DMA 0 current link descriptor address register R/W 0x0000_0000 15.3.2.3/15-14 0x2_1110 SATRn—DMA 0 source attributes register R/W 0x0000_0000 15.3.2.4/15-16 0x2_1114 SARn—DMA 0 source address register R/W 0x0000_0000 15.3.2.5/15-18 0x2_1118 DATRn—DMA 0 destination attributes register R/W 0x0000_0000 15.3.2.6/15-19 0x2_111C DARn—DMA 0 destination address register R/W 0x0000_0000 15.3.2.7/15-21 0x2_1120 BCRn—DMA 0 byte count register R/W 0x0000_0000 15.3.2.8/15-23 0x2_1124 Reserved — — — 0x2_1128 NLNDARn—DMA 0 next link descriptor address register R/W 0x0000_0000 15.3.2.9/15-23 0x2_1130 Reserved — — — 0x2_1134 CLSDARn—DMA 0 current list alternate base descriptor address register R/W 0x0000_0000 15.3.2.10/15-24 0x2_1138 Reserved — — — 0x2_113C NLSDARn—DMA 0 next list descriptor address register R/W 0x0000_0000 15.3.2.11/15-25 0x2_1140 SSRn—DMA 0 source stride register R/W 0x0000_0000 15.3.2.12/15-25 0x2_1144 DSRn—DMA 0 destination stride register R/W 0x0000_0000 15.3.2.13/15-26 Table 2-9. Memory Map (continued) Offset Register Access Reset Section/Page |
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