MPC8540 datasheet(61/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

lxi

Figures

Figure

Number

Title

Page

Number

21-17

TBDLEN Register Definition ............................................................................................. 21-27

21-18

CTBPTR Register Definition .............................................................................................. 21-27

21-19

TBPTR Register Definition................................................................................................. 21-28

21-20

TBASE Register Definition ................................................................................................ 21-28

21-21

OSTBD Register Definition................................................................................................ 21-29

21-22

OSTBDP Register Definition.............................................................................................. 21-31

21-23

RCTRL Register Definition ................................................................................................ 21-31

21-24

RSTAT Register Definition ................................................................................................. 21-32

21-25

RBDLEN Register Definition ............................................................................................. 21-33

21-26

CRBPTR Register Definition.............................................................................................. 21-34

21-27

MRBLR Register Definition ............................................................................................... 21-34

21-28

Receive Buffer Descriptor Pointer Definition..................................................................... 21-35

21-29

RBASE Register Definition ................................................................................................ 21-35

21-30

MACCFG1 Register Definition .......................................................................................... 21-38

21-31

MACCFG2 Register Definition .......................................................................................... 21-40

21-32

IPGIFG Register Definition ................................................................................................ 21-41

21-33

Half-Duplex Register Definition......................................................................................... 21-41

21-34

Maximum Frame Length Register Definition..................................................................... 21-42

21-35

Interface Status Register Definition .................................................................................... 21-43

21-36

Station Address Part 1 Register Definition ......................................................................... 21-44

21-37

Station Address Part 2 Register Definition ......................................................................... 21-44

21-38

IADDRn Register Definition .............................................................................................. 21-45

21-39

GADDRn Register Definition............................................................................................. 21-46

21-40

ATTR Register Definition ................................................................................................... 21-47

21-41

ATTRELI Register Definition............................................................................................. 21-48

21-42

FEC–MII Connection.......................................................................................................... 21-49

21-43

Ethernet Address Recognition Flowchart ........................................................................... 21-56

21-44

Example of FEC Memory Structure for BD ....................................................................... 21-64

21-45

Buffer Descriptor Ring........................................................................................................ 21-64

21-46

Transmit Buffer Descriptor ................................................................................................. 21-65

21-47

Receive Buffer Descriptor................................................................................................... 21-67

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