MPC8540 datasheet(59/1302 Pages) FREESCALE

59 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

lix

Figures

Figure

Number

Title

Page

Number

17-78

Port-Write Mode Register (PWMR) ................................................................................... 17-81

17-79

Port-Write Status Register (PWSR) .................................................................................... 17-82

17-80

Port-Write Queue Base Address Register (PWQBAR) ...................................................... 17-83

17-81

Physical Maintenance Field (PMF) Definition ................................................................... 17-86

17-82

Outbound Message Queue Structure................................................................................. 17-113

17-83

Descriptor Dequeue Pointer and Descriptor ..................................................................... 17-116

17-84

Inbound Mailbox Structure ............................................................................................... 17-117

17-85

Inbound Doorbell Queue and Pointer Structure................................................................ 17-119

17-86

Doorbell Entry Format ...................................................................................................... 17-120

17-87

Inbound Port-Write Structure............................................................................................ 17-122

18-1

POR PLL Status Register (PORPLLSR) .............................................................................. 18-4

18-2

POR Boot Mode Status Register (PORBMSR) .................................................................... 18-5

18-3

POR I/O Impedance Status and Control Register (PORIMPSCR)....................................... 18-6

18-4

POR Device Status Register (PORDEVSR) ......................................................................... 18-8

18-5

POR Debug Mode Status Register (PORDBGMSR) ........................................................... 18-9

18-6

POR Configuration Register (GPPORCR) ........................................................................... 18-9

18-7

General-Purpose I/O Control Register (GPIOCR).............................................................. 18-10

18-8

General-Purpose Output Data Register (GPOUTDR) ........................................................ 18-11

18-9

General-Purpose Output Data Register (GPINDR) ............................................................ 18-12

18-10

Alternate Function Pin Multiplex Control Register (PMUXCR) ....................................... 18-13

18-11

Device Disable Register (DEVDISR)................................................................................. 18-13

18-12

Power Management Control and Status Register (POWMGTCSR) .................................. 18-15

18-13

Machine Check Summary Register (MCPSUMR) ............................................................. 18-17

18-14

Processor Version Register (PVR) ...................................................................................... 18-17

18-15

System Version Register (SVR).......................................................................................... 18-18

18-16

Clock Out Control Register (CLKOCR)............................................................................. 18-18

18-17

DDR DLL Control Register (DDRDLLCR)....................................................................... 18-19

18-18

Local Bus DLL Control Register (LBDLLCR) .................................................................. 18-20

18-19

e500 Core Power Management State Diagram ................................................................... 18-21

18-20

MPC8540 Power Management Handshaking Signals ........................................................ 18-26

19-1

Performance Monitor Block Diagram................................................................................... 19-2

19-2

Performance Monitor Global Control Register (PMGC0).................................................... 19-5

19-3

Performance Monitor Local Control Register A0 (PMLCA0) ............................................. 19-6

19-4

Performance Monitor Local Control Registers A1–A8 (PMLCA1–PMLCA8) ................... 19-6

19-5

Performance Monitor Local Control Register B0 (PMLCB0).............................................. 19-7

19-6

Performance Monitor Local Control Registers B1–B8 (PMLCB1–PMLCB8).................... 19-8

19-7

Performance Monitor Counter Register 0 (PMC0)............................................................. 19-10

19-8

Performance Monitor Counter Registers 1–8 (PMC1–PMC8)........................................... 19-10

19-9

Duration Threshold Event Sequence Timing Diagram ....................................................... 19-12

19-10

Burst Size, Distance, Granularity, and Burstiness Counting............................................... 19-13

MPC8540 датащи(PDF) 59 Page - Freescale Semiconductor, Inc

MPC8540 датащи(HTML) 59 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL