MPC8540 datasheet(54/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

liv

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

14-109

TBI Control Register Definition ....................................................................................... 14-102

14-110

TSEC-MII Connection ...................................................................................................... 14-104

14-111

TSEC-GMII Connection ................................................................................................... 14-105

14-112

TSEC-RGMII Connection ................................................................................................ 14-106

14-113

TSEC-TBI Connection...................................................................................................... 14-107

14-114

TSEC-RTBI Connection ................................................................................................... 14-108

14-115

Ethernet Address Recognition Flowchart ......................................................................... 14-117

14-116

Example of TSEC Memory Structure for BD................................................................... 14-126

14-117

Buffer Descriptor Ring...................................................................................................... 14-126

14-118

Transmit Buffer Descriptor ............................................................................................... 14-127

14-119

Receive Buffer Descriptor................................................................................................. 14-129

15-1

DMA Block Diagram............................................................................................................ 15-1

15-2

DMA Operational Flow Chart .............................................................................................. 15-4

15-3

DMA Signal Summary.......................................................................................................... 15-5

15-4

DMA Register Space (Memory-Mapped)............................................................................. 15-7

15-5

DMA Mode Registers (MRn) ............................................................................................. 15-10

15-6

Status Registers (SRn) ........................................................................................................ 15-13

15-7

Basic Chaining Mode Flow Chart....................................................................................... 15-15

15-8

Current Link Descriptor Address Registers (CLNDARn) .................................................. 15-16

15-9

Source Attributes Registers (SATRn) ................................................................................. 15-17

15-10

Source Address Registers (SARn) ...................................................................................... 15-18

15-11

Source Address Registers for RapidIO Maintenance Reads (SARn) ................................. 15-19

15-12

Destination Attributes Registers (DATRn) ......................................................................... 15-20

15-13

Destination Address Registers (DARn) .............................................................................. 15-21

15-14

Destination Address Registers for RapidIO Maintenance Writes (DARn)......................... 15-22

15-15

Byte Count Registers (BCRn)............................................................................................. 15-23

15-16

Next Link Descriptor Address Registers (NLNDARn) ...................................................... 15-23

15-17

Current List Descriptor Address Registers (CLSDARn) .................................................... 15-24

15-18

Next List Descriptor Address Registers (NLSDARn) ........................................................ 15-25

15-19

Source Stride Registers (SSRn) .......................................................................................... 15-25

15-20

Destination Stride Registers (DSRn) .................................................................................. 15-26

15-21

DMA General Status Register (DGSR) .............................................................................. 15-27

15-22

External Control Interface Timing ...................................................................................... 15-34

15-23

Stride Size and Stride Distance ........................................................................................... 15-37

15-24

DMA Transaction Flow with DMA Descriptors ................................................................ 15-39

15-25

List Descriptor Format ........................................................................................................ 15-40

15-26

Link Descriptor Format....................................................................................................... 15-40

15-27

DMA Data Paths ................................................................................................................. 15-42

16-1

PCI/X Controller Block Diagram ......................................................................................... 16-2

16-2

PCI/X Interface External Signals .......................................................................................... 16-7

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