MPC8540 datasheet(11/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

6.11

L1 Cache Configuration Registers................................................................................. 6-30

6.11.1

L1 Cache Control and Status Register 0 (L1CSR0) .................................................. 6-30

6.11.2

L1 Cache Control and Status Register 1 (L1CSR1) .................................................. 6-31

6.11.3

L1 Cache Configuration Register 0 (L1CFG0) ......................................................... 6-32

6.11.4

L1 Cache Configuration Register 1 (L1CFG1) ......................................................... 6-33

6.12

MMU Registers.............................................................................................................. 6-34

6.12.1

Process ID Registers (PID0–PID2)............................................................................ 6-34

6.12.2

MMU Control and Status Register 0 (MMUCSR0) .................................................. 6-34

6.12.3

MMU Configuration Register (MMUCFG) .............................................................. 6-35

6.12.4

TLB Configuration Registers (TLBnCFG)................................................................ 6-35

6.12.4.1

TLB0 Configuration Register 0 (TLB0CFG) ........................................................ 6-35

6.12.4.2

TLB1 Configuration Register 1 (TLB1CFG) ........................................................ 6-36

6.12.5

MMU Assist Registers............................................................................................... 6-37

6.12.5.1

MAS Register 0 (MAS0) ....................................................................................... 6-37

6.12.5.2

MAS Register 1 (MAS1) ....................................................................................... 6-38

6.12.5.3

MAS Register 2 (MAS2) ....................................................................................... 6-39

6.12.5.4

MAS Register 3 (MAS3) ....................................................................................... 6-40

6.12.5.5

MAS Register 4 (MAS4) ....................................................................................... 6-40

6.12.5.6

MAS Register 6 (MAS6) ....................................................................................... 6-41

6.13

Debug Registers .............................................................................................................6-42

6.13.1

Debug Control Registers (DBCR0–DBCR2) ............................................................ 6-42

6.13.1.1

Debug Control Register 0 (DBCR0)...................................................................... 6-42

6.13.1.2

Debug Control Register 1 (DBCR1)...................................................................... 6-43

6.13.1.3

Debug Control Register 2 (DBCR2)...................................................................... 6-45

6.13.2

Debug Status Register (DBSR).................................................................................. 6-46

6.13.3

Instruction Address Compare Registers (IAC1–IAC2) ............................................. 6-47

6.13.4

Data Address Compare Registers (DAC1–DAC2).................................................... 6-48

6.14

Signal Processing and Embedded Floating-Point Status and

Control Register (SPEFSCR) .................................................................................... 6-48

6.14.1

Accumulator (ACC)................................................................................................... 6-50

6.15

Performance Monitor Registers (PMRs) ....................................................................... 6-51

6.15.1

Global Control Register 0 (PMGC0, UPMGC0)....................................................... 6-52

6.15.2

Local Control A Registers

(PMLCa0–PMLCa3, UPMLCa0–UPMLCa3) ...................................................... 6-52

6.15.3

Local Control B Registers

(PMLCb0–PMLCb3, UPMLCb0–UPMLCb3) ..................................................... 6-53

6.15.4

Performance Monitor Counter Registers

(PMC0–PMC3, UPMC0–UPMC3) ....................................................................... 6-54

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