MPC8540 datasheet(85/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

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Chapter 13, “Local Bus Controller,” describes the local bus controller of the MPC8540.

The main component of the local bus controller (LBC) is its memory controller which

provides a seamless interface to many types of memory devices and peripherals. The

memory controller is responsible for controlling eight memory banks shared by a high

performance SDRAM machine, a general-purpose chip-select machine (GPCM), and up to

three user-programmable machines (UPMs). As such, it supports a minimal glue logic

interface to synchronous DRAM (SDRAM), SRAM, EPROM, flash EPROM, burstable

RAM, regular DRAM devices, extended data output DRAM devices, and other peripherals.

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Chapter 14, “Three-Speed Ethernet Controllers,” describes the 2 three-speed Ethernet

controllers on the MPC8540. These controllers provide 10/100/1000 Mbps Ethernet

support with a complete set of media-independent interface options including GMII,

RGMII, TBI, and RTBI. Each controller provides very high throughput using a captive

DMA channel and direct connection to the MPC8540 memory coherency module.

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Chapter 15, “DMA Controller,” describes the four-channel general-purpose DMA

controller of the MPC8540. The DMA controller transfers blocks of data, independent of

the e500 core or external hosts. Data movement occurs among RapidIO and the local

address space. The DMA controller has four high-speed channels. Both the e500 core and

external masters can initiate a DMA transfer. All channels are capable of complex data

movement and advanced transaction chaining.

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Chapter 16, “PCI/PCI-X Bus Interface,” describes the PCI/PCI-X controller of the

MPC8540.

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Chapter 17, “RapidIO Interface,” describes the RapidIO controller of the MPC8540.

Part IV, “Global Functions and Debug,” defines other global blocks of the MPC8540. The

following chapters are included:

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Chapter 18, “Global Utilities,” defines the global utilities of the MPC8540. These include

power management, I/O device enabling, power-on-reset (POR) configuration monitoring,

general-purpose I/O signal use, and multiplexing for the interrupt and local bus chip select

signals

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Chapter 19, “Performance Monitor,” describes the performance monitor of the MPC8540.

Note that the MPC8540 performance monitor is similar to but separate from the

performance monitor implemented on the e500 core.

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Chapter 20, “Debug Features and Watchpoint Facility,” describes the debug features and

watchpoint monitor of the MPC8540.

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Chapter 21, “10/100 Fast Ethernet Controller,” includes information about using the

dual-speed Ethernet controller of the MPC8540 for debug purposes.

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Appendix A, “Revision History,” lists the major differences between revisions of the

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual.

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