MPC8540 datasheet(40/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

21.5

Memory Map/Register Definition ................................................................................. 21-9

21.5.1

Top-Level Module Memory Map .............................................................................. 21-9

21.5.2

Detailed Memory Map............................................................................................. 21-10

21.5.3

Memory-Mapped Register Descriptions.................................................................. 21-13

21.5.3.1

FEC General Control and Status Registers.......................................................... 21-13

21.5.3.1.1

Interrupt Event Register (IEVENT) ................................................................ 21-13

21.5.3.1.2

Interrupt Mask Register (IMASK) .................................................................. 21-16

21.5.3.1.3

Error Disabled Register (EDIS)....................................................................... 21-18

21.5.3.1.4

Minimum Frame Length Register (MINFLR)................................................. 21-18

21.5.3.1.5

Pause Time Value Register (PTV) ................................................................... 21-19

21.5.3.1.6

DMA Control Register (DMACTRL) ............................................................. 21-20

21.5.3.2

FEC FIFO Control and Status Registers.............................................................. 21-21

21.5.3.2.1

FIFO Pause Control Register (FIFO_PAUSE_CTRL).................................... 21-22

21.5.3.2.2

FIFO Transmit Threshold Register (FIFO_TX_THR) .................................... 21-23

21.5.3.2.3

FIFO Transmit Starve Register (FIFO_TX_STARVE) ................................... 21-24

21.5.3.2.4

FIFO Transmit Starve Shutoff Register

(FIFO_TX_STARVE_SHUTOFF).............................................................. 21-24

21.5.3.3

FEC Transmit Control and Status Registers ........................................................ 21-25

21.5.3.3.1

Transmit Control Register (TCTRL) ............................................................... 21-25

21.5.3.3.2

Transmit Status Register (TSTAT) .................................................................. 21-26

21.5.3.3.3

TxBD Data Length Register (TBDLEN)......................................................... 21-27

21.5.3.3.4

Current Transmit Buffer Descriptor Pointer Register (CTBPTR) ................... 21-27

21.5.3.3.5

Transmit Buffer Descriptor Pointer Register (TBPTR) ................................... 21-28

21.5.3.3.6

Transmit Descriptor Base Address Register (TBASE) ................................... 21-28

21.5.3.3.7

Out-of-Sequence TxBD Register (OSTBD).................................................... 21-29

21.5.3.3.8

Out-of-Sequence Tx Data Buffer Pointer Register (OSTBDP)....................... 21-31

21.5.3.4

FEC Receive Control and Status Registers ......................................................... 21-31

21.5.3.4.1

Receive Control Register (RCTRL) ................................................................ 21-31

21.5.3.4.2

Receive Status Register (RSTAT).................................................................... 21-32

21.5.3.4.3

RxBD Data Length Register (RBDLEN) ........................................................ 21-33

21.5.3.4.4

Current Receive Buffer Descriptor Pointer Register (CRBPTR) .................... 21-33

21.5.3.4.5

Maximum Receive Buffer Length Register (MRBLR) ................................... 21-34

21.5.3.4.6

Receive Buffer Descriptor Pointer Register (RBPTR) .................................... 21-35

21.5.3.4.7

Receive Descriptor Base Address Register (RBASE)..................................... 21-35

21.5.3.5

MAC Functionality.............................................................................................. 21-36

21.5.3.5.1

Configuring the MAC...................................................................................... 21-36

21.5.3.5.2

Controlling CSMA/CD.................................................................................... 21-36

21.5.3.5.3

Handling Packet Collisions ............................................................................. 21-36

21.5.3.5.4

Controlling Packet Flow .................................................................................. 21-37

21.5.3.6

MAC Registers .................................................................................................... 21-38

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