MPC8540 datasheet(15/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

9.5.11

Error Checking and Correcting (ECC) ...................................................................... 9-46

9.5.12

Error Management ..................................................................................................... 9-48

9.6

Initialization/Application Information ........................................................................... 9-49

9.6.1

DDR SDRAM Initialization Sequence ...................................................................... 9-50

Chapter 10

Programmable Interrupt Controller

10.1

Introduction.................................................................................................................... 10-1

10.1.1

Overview.................................................................................................................... 10-2

10.1.2

Features ...................................................................................................................... 10-3

10.1.3

Interrupts to the Processor Core................................................................................. 10-4

10.1.4

Modes of Operation ................................................................................................... 10-5

10.1.4.1

Mixed Mode (GCR[M] = 1) .................................................................................. 10-5

10.1.4.2

Pass-Through Mode (GCR[M] = 0) ...................................................................... 10-6

10.1.5

Interrupt Sources........................................................................................................ 10-6

10.1.5.1

Interrupt Routing—Mixed Mode........................................................................... 10-7

10.1.5.2

Internal Interrupt Sources ...................................................................................... 10-7

10.2

External Signal Descriptions ......................................................................................... 10-8

10.2.1

Signal Overview ........................................................................................................ 10-8

10.2.2

Detailed Signal Descriptions ..................................................................................... 10-8

10.3

Memory Map/Register Definition ................................................................................. 10-9

10.3.1

Global Registers....................................................................................................... 10-16

10.3.1.1

Feature Reporting Register (FRR)....................................................................... 10-16

10.3.1.2

Global Configuration Register (GCR)................................................................. 10-17

10.3.1.3

Vendor Identification Register (VIR) .................................................................. 10-17

10.3.1.4

Processor Initialization Register (PIR) ................................................................ 10-18

10.3.1.5

IPI Vector/Priority Registers (IPIVPRn) ............................................................. 10-19

10.3.1.6

Spurious Vector Register (SVR).......................................................................... 10-19

10.3.2

Global Timer Registers ............................................................................................ 10-20

10.3.2.1

Timer Frequency Reporting Register (TFRR)..................................................... 10-20

10.3.2.2

Global Timer Current Count Registers (GTCCRn) ............................................. 10-21

10.3.2.3

Global Timer Base Count Registers (GTBCRn) ................................................. 10-21

10.3.2.4

Global Timer Vector/Priority Registers (GTVPRn) ............................................ 10-22

10.3.2.5

Global Timer Destination Registers (GTDRn) .................................................... 10-23

10.3.2.6

Timer Control Register (TCR)............................................................................. 10-24

10.3.3

IRQ_OUT and Critical Interrupt Summary Registers ............................................. 10-26

10.3.3.1

IRQ_OUT Summary Register 0 (IRQSR0) ......................................................... 10-26

10.3.3.2

IRQ_OUT Summary Register 1 (IRQSR1) ......................................................... 10-27

10.3.3.3

Critical Interrupt Summary Register 0 (CISR0).................................................. 10-27

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