MPC8540 datasheet(45/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

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Figures

Figure

Number

Title

Page

Number

6-43

MAS Register 1 (MAS1) ...................................................................................................... 6-38

6-44

MAS Register 2 (MAS2) ...................................................................................................... 6-39

6-45

MAS Register 3 (MAS3) ...................................................................................................... 6-40

6-46

MAS Register 4 (MAS4) ...................................................................................................... 6-40

6-47

MAS Register 6 (MAS6) ...................................................................................................... 6-41

6-48

Debug Control Register 0 (DBCR0) ..................................................................................... 6-42

6-49

Debug Control Register 1 (DBCR1) ..................................................................................... 6-43

6-50

Debug Control Register 2 (DBCR2) ..................................................................................... 6-45

6-51

Debug Status Register (DBSR)............................................................................................. 6-46

6-52

Instruction Address Compare Registers (IAC1–IAC2) ........................................................ 6-47

6-53

Data Address Compare Registers (DAC1–DAC2) ............................................................... 6-48

6-54

Signal Processing and Embedded Floating-Point Status and Control

Register (SPEFSCR) ........................................................................................................ 6-48

6-55

Accumulator (ACC) .............................................................................................................. 6-50

6-56

Performance Monitor Global Control Register 0 (PMGC0),

User Performance Monitor Global Control Register 0 (UPMGC0) ................................ 6-52

6-57

Local Control A Registers (PMLCa0–PMLCa3),

User Local Control A Registers (UPMLCa0–UPMLCa3) .............................................. 6-52

6-58

Local Control B Registers (PMLCb0–PMLCb3),

User Local Control B Registers (UPMLCb0–UPMLCb3) .............................................. 6-53

6-59

Performance Monitor Counter Registers (PMC0–PMC3),

User Performance Monitor Counter Registers (UPMC0–UPMC3)................................. 6-54

7-1

L2 Cache/SRAM Configuration ............................................................................................. 7-1

7-2

Cache Organization ................................................................................................................. 7-3

7-3

256-Kbyte L2 Cache Address Configuration—Full Cache Mode.......................................... 7-4

7-4

128-Kbyte L2 Cache Address Configuration—Half SRAM, Half Cache Mode.................... 7-5

7-5

Data Bus Connection of CCB ................................................................................................. 7-5

7-6

Address Bus Connection of CCB............................................................................................ 7-6

7-7

L2 Control Register (L2CTL) ................................................................................................. 7-7

7-8

L2 Cache External Write Address Registers (L2CEWARn)................................................. 7-10

7-9

L2 Cache External Write Control Registers (L2CEWCR0–L2CEWCR3)........................... 7-10

7-10

L2 Memory-Mapped SRAM Base Address Registers (L2SRBARn)................................... 7-11

7-11

L2 Error Injection Mask High Register (L2ERRINJHI) ...................................................... 7-13

7-12

L2 Error Injection Mask Low Register (L2ERRINJLO) ...................................................... 7-14

7-13

L2 Error Injection Mask Control Register (L2ERRINJCTL) ............................................... 7-14

7-14

L2 Error Capture Data High Register (L2CAPTDATAHI)................................................... 7-15

7-15

L2 Error Capture Data Low Register (L2CAPTDATALO) .................................................. 7-15

7-16

L2 Error Syndrome Register (L2CAPTECC) ....................................................................... 7-16

7-17

L2 Error Detect Register (L2ERRDET) ............................................................................... 7-16

7-18

L2 Error Disable Register (L2ERRDIS) ............................................................................... 7-17

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