MPC8540 datasheet(17/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xvii

Contents

Paragraph

Number

Title

Page

Number

11.1

Introduction.................................................................................................................... 11-1

11.1.1

Overview.................................................................................................................... 11-2

11.1.2

Features ...................................................................................................................... 11-2

11.1.3

Modes of Operation ................................................................................................... 11-2

11.2

External Signal Descriptions ......................................................................................... 11-3

11.2.1

Signal Overview ........................................................................................................ 11-3

11.2.2

Detailed Signal Descriptions ..................................................................................... 11-3

11.3

Memory Map/Register Definition ................................................................................. 11-4

11.3.1

Register Descriptions ................................................................................................. 11-4

11.3.1.1

I2C Address Register (I2CADR) ........................................................................... 11-5

11.3.1.2

I2C Frequency Divider Register (I2CFDR)........................................................... 11-5

11.3.1.3

I2C Control Register (I2CCR) ............................................................................... 11-6

11.3.1.4

I2C Status Register (I2CSR) .................................................................................. 11-7

11.3.1.5

I2C Data Register (I2CDR).................................................................................... 11-9

11.3.1.6

Digital Filter Sampling Rate Register (I2CDFSRR) ........................................... 11-10

11.4

Functional Description................................................................................................. 11-10

11.4.1

Transaction Protocol ................................................................................................ 11-10

11.4.1.1

START Condition .................................................................................................11-11

11.4.1.2

Slave Address Transmission .................................................................................11-11

11.4.1.3

Repeated START Condition ................................................................................ 11-12

11.4.1.4

STOP Condition................................................................................................... 11-12

11.4.1.5

Protocol Implementation Details ......................................................................... 11-13

11.4.1.5.1

Transaction Monitoring—Implementation Details.......................................... 11-13

11.4.1.5.2

Control Transfer—Implementation Details ..................................................... 11-13

11.4.1.6

Address Compare—Implementation Details ....................................................... 11-14

11.4.2

Arbitration Procedure .............................................................................................. 11-14

11.4.2.1

Arbitration Control .............................................................................................. 11-15

11.4.3

Handshaking ............................................................................................................ 11-15

11.4.4

Clock Control........................................................................................................... 11-15

11.4.4.1

Clock Synchronization......................................................................................... 11-16

11.4.4.2

Input Synchronization and Digital Filter ............................................................. 11-16

11.4.4.2.1

Input Signal Synchronization .......................................................................... 11-16

11.4.4.2.2

Filtering of SCL and SDA Lines ..................................................................... 11-16

11.4.4.3

Clock Stretching .................................................................................................. 11-17

11.4.5

Boot Sequencer Mode.............................................................................................. 11-17

11.4.5.1

EEPROM Calling Address .................................................................................. 11-17

11.4.5.2

EEPROM Data Format ........................................................................................ 11-18

11.5

Initialization/Application Information ......................................................................... 11-20

11.5.1

Initialization Sequence............................................................................................. 11-20

11.5.2

Generation of START .............................................................................................. 11-21

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