MPC8540 datasheet(29/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xxix

Contents

Paragraph

Number

Title

Page

Number

16.1.3.1.2

Agent Mode ....................................................................................................... 16-6

16.1.3.1.3

Agent Configuration Lock Mode ...................................................................... 16-6

16.1.3.2

PCI/X Bus Width (64-/32-Bit Bus) ....................................................................... 16-6

16.1.3.3

PCI/X Arbiter (Internal/External Arbiter) ............................................................. 16-6

16.1.3.4

PCI/X Bus Mode.................................................................................................... 16-6

16.1.3.5

PCI/X Signal Output Hold Timing ........................................................................ 16-6

16.1.3.6

PCI/X Impedance................................................................................................... 16-7

16.2

External Signal Descriptions ......................................................................................... 16-7

16.3

Memory Map/Register Definitions .............................................................................. 16-15

16.3.1

PCI/X Memory Mapped Registers .......................................................................... 16-15

16.3.1.1

PCI/X Configuration Access Registers ............................................................... 16-18

16.3.1.1.1

PCI/X Configuration Address Register (CFG_ADDR) .................................. 16-18

16.3.1.1.2

PCI/X Configuration Data Register (CFG_DATA) ......................................... 16-19

16.3.1.1.3

PCI/X Interrupt Acknowledge Register (INT_ACK)...................................... 16-20

16.3.1.2

PCI/X ATMU Outbound Registers ...................................................................... 16-20

16.3.1.2.1

PCI/X Outbound Translation Address Registers (POTARn) .......................... 16-21

16.3.1.2.2

PCI/X Outbound Translation Extended Address Registers

(POTEARn) ................................................................................................. 16-21

16.3.1.2.3

PCI/X Outbound Window Base Address Registers (POWBARn).................. 16-22

16.3.1.2.4

PCI/X Outbound Window Attributes Registers (POWARn)........................... 16-22

16.3.1.3

PCI/X ATMU Inbound Registers......................................................................... 16-24

16.3.1.3.1

PCI/X Inbound Translation Address Registers (PITARn)............................... 16-25

16.3.1.3.2

PCI/X Inbound Window Base Address Registers (PIWBARn) ...................... 16-25

16.3.1.3.3

PCI/X Inbound Window Base Extended Address Registers

(PIWBEARn) .............................................................................................. 16-26

16.3.1.3.4

PCI/X Inbound Window Attributes Registers (PIWARn) ............................... 16-26

16.3.1.4

PCI/X Error Management Registers .................................................................... 16-28

16.3.1.4.1

PCI/X Error Detect Register (ERR_DR)......................................................... 16-29

16.3.1.4.2

PCI/X Error Capture Disable Register (ERR_CAP_DR)................................ 16-30

16.3.1.4.3

PCI/X Error Enable Register (ERR_EN) ........................................................ 16-31

16.3.1.4.4

PCI/X Error Attributes Capture Register (ERR_ATTRIB) ............................. 16-32

16.3.1.4.5

PCI/X Error Address Capture Register (ERR_ADDR)................................... 16-33

16.3.1.4.6

PCI/X Error Extended Address Capture Register

(ERR_EXT_ADDR).................................................................................... 16-34

16.3.1.4.7

PCI/X Error Data Low Capture Register (ERR_DL) ...................................... 16-34

16.3.1.4.8

PCI/X Error Data High Capture Register (ERR_DH)..................................... 16-34

16.3.1.4.9

PCI/X Gasket Timer Register (GAS_TIMR) .................................................. 16-35

16.3.1.4.10

PCI-X Split Completion Timer Register (PCIX_TIMR)................................. 16-36

16.3.2

PCI/X Configuration Header ................................................................................... 16-36

16.3.2.1

PCI Vendor ID Register—Offset 0x00 ................................................................ 16-37

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