MPC8540 datasheet(19/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xix

Contents

Paragraph

Number

Title

Page

Number

12.4.2

Baud-Rate Generator Logic ..................................................................................... 12-22

12.4.3

Local Loop-Back Mode ........................................................................................... 12-22

12.4.4

Errors ....................................................................................................................... 12-23

12.4.4.1

Framing Error ...................................................................................................... 12-23

12.4.4.2

Parity Error .......................................................................................................... 12-23

12.4.4.3

Overrun Error....................................................................................................... 12-23

12.4.5

FIFO Mode .............................................................................................................. 12-24

12.4.5.1

FIFO Interrupts .................................................................................................... 12-24

12.4.5.2

DMA Mode Select ............................................................................................... 12-24

12.4.5.3

Interrupt Control Logic........................................................................................ 12-25

12.5

DUART Initialization/Application Information .......................................................... 12-25

Chapter 13

Local Bus Controller

13.1

Introduction.................................................................................................................... 13-1

13.1.1

Overview.................................................................................................................... 13-2

13.1.2

Features ...................................................................................................................... 13-2

13.1.3

Modes of Operation ................................................................................................... 13-3

13.1.3.1

LBC Bus Clock and Clock Ratios ......................................................................... 13-4

13.1.3.2

Source ID Debug Mode ......................................................................................... 13-4

13.1.4

Power-Down Mode.................................................................................................... 13-4

13.1.5

References.................................................................................................................. 13-4

13.2

External Signal Descriptions ......................................................................................... 13-5

13.3

Memory Map/Register Definition ................................................................................. 13-9

13.3.1

Register Descriptions ............................................................................................... 13-10

13.3.1.1

Base Registers (BR0–BR7) ................................................................................. 13-11

13.3.1.2

Option Registers (OR0–OR7).............................................................................. 13-12

13.3.1.2.1

Address Mask .................................................................................................. 13-13

13.3.1.2.2

Option Registers (ORn)—GPCM Mode ......................................................... 13-14

13.3.1.2.3

Option Registers (ORn)—UPM Mode ............................................................ 13-16

13.3.1.2.4

Option Registers (ORn)—SDRAM Mode ...................................................... 13-17

13.3.1.3

UPM Memory Address Register (MAR)............................................................. 13-18

13.3.1.4

UPM Mode Registers (MxMR) ........................................................................... 13-19

13.3.1.5

Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 13-21

13.3.1.6

UPM Data Register (MDR) ................................................................................. 13-22

13.3.1.7

SDRAM Machine Mode Register (LSDMR) ...................................................... 13-22

13.3.1.8

UPM Refresh Timer (LURT)............................................................................... 13-24

13.3.1.9

SDRAM Refresh Timer (LSRT).......................................................................... 13-25

13.3.1.10

Transfer Error Status Register (LTESR).............................................................. 13-26

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