MPC8540 datasheet(16/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

xvi

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

10.3.3.4

Critical Interrupt Summary Register 1 (CISR1).................................................. 10-28

10.3.4

Performance Monitor Mask Registers (PMMRs).................................................... 10-28

10.3.4.1

Performance Monitor Mask Register (Lower) (PMnMR0)................................. 10-29

10.3.4.2

Performance Monitor Mask Registers (Upper) (PMnMR1)................................ 10-30

10.3.5

Message Registers.................................................................................................... 10-30

10.3.5.1

Message Registers (MSGR0–MSGR3) ............................................................... 10-30

10.3.5.2

Message Enable Register (MER)......................................................................... 10-31

10.3.5.3

Message Status Register (MSR) .......................................................................... 10-31

10.3.6

Interrupt Source Configuration Registers ................................................................ 10-32

10.3.6.1

External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ..................... 10-32

10.3.6.2

External Interrupt Destination Registers (EIDR0–EIDR11) ............................... 10-33

10.3.6.3

Internal Interrupt Vector/Priority Registers (IIVPR0–IIVPR31)......................... 10-34

10.3.6.4

Internal Interrupt Destination Registers (IIDR0–IIDR31) .................................. 10-35

10.3.6.5

Messaging Interrupt Vector/Priority Registers (MIVPR0–MIVPR3) ................. 10-36

10.3.6.6

Messaging Interrupt Destination Registers (MIDR0–MIDR3) ........................... 10-37

10.3.7

Per-CPU Registers ................................................................................................... 10-38

10.3.7.1

Interprocessor Interrupt Dispatch Register (IPIDR0–IPIDR3) ........................... 10-39

10.3.7.2

Processor Current Task Priority Register (CTPR)............................................... 10-40

10.3.7.3

Who Am I Register (WHOAMI) ......................................................................... 10-41

10.3.7.4

Processor Interrupt Acknowledge Register (IACK)............................................ 10-41

10.3.7.5

Processor End of Interrupt Register (EOI) .......................................................... 10-42

10.4

Functional Description................................................................................................. 10-43

10.4.1

Flow of Interrupt Control......................................................................................... 10-43

10.4.1.1

Interrupt Source Priority ...................................................................................... 10-45

10.4.1.2

Processor Current Task Priority........................................................................... 10-45

10.4.1.3

Interrupt Acknowledge ........................................................................................ 10-46

10.4.2

Nesting of Interrupts ................................................................................................ 10-46

10.4.3

Processor Initialization ............................................................................................ 10-46

10.4.4

Spurious Vector Generation ..................................................................................... 10-46

10.4.5

Messaging Interrupts................................................................................................ 10-47

10.4.6

Global Timers .......................................................................................................... 10-47

10.4.7

Reset of the PIC ....................................................................................................... 10-47

10.5

Initialization/Application Information ......................................................................... 10-48

10.5.1

Programming Guidelines ......................................................................................... 10-48

10.5.1.1

PIC Registers ....................................................................................................... 10-48

10.5.1.2

Changing Interrupt Source Configuration ........................................................... 10-50

Chapter 11

I2C Interface

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