MPC8540 datasheet(52/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

lii

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

14-29

RBDLEN Register Definition ............................................................................................. 14-42

14-30

RXIC Register Definition ................................................................................................... 14-43

14-31

CRBPTR Register Definition.............................................................................................. 14-44

14-32

MRBL Register Definition.................................................................................................. 14-44

14-33

RBPTR Register Definition ................................................................................................ 14-45

14-34

RBASE Register Definition ................................................................................................ 14-46

14-35

MACCFG1 Register Definition .......................................................................................... 14-49

14-36

MACCFG2 Register Definition .......................................................................................... 14-51

14-37

IPGIFG Register Definition ................................................................................................ 14-52

14-38

Half-Duplex Register Definition......................................................................................... 14-53

14-39

Maximum Frame Length Register Definition..................................................................... 14-54

14-40

MII Management Configuration Register Definition ......................................................... 14-54

14-41

MIIMCOM Register Definition .......................................................................................... 14-55

14-42

MIIMADD Register Definition .......................................................................................... 14-56

14-43

MII Management Control Register Definition.................................................................... 14-57

14-44

MIIMSTAT Register Definition .......................................................................................... 14-57

14-45

MII Management Indicator Register Definition ................................................................. 14-58

14-46

Interface Status Register Definition .................................................................................... 14-58

14-47

Station Address Part 1 Register Definition ......................................................................... 14-59

14-48

Station Address Part 2 Register Definition ......................................................................... 14-60

14-49

Transmit and Receive 64-Byte Frame Register Definition ................................................. 14-61

14-50

Transmit and Receive 65- to 127-Byte Frame Register Definition .................................... 14-61

14-51

Transmit and Receive 128- to 255-Byte Frame Register Definition .................................. 14-62

14-52

Transmit and Receive 256- to 511-Byte Frame Register Definition................................... 14-62

14-53

Transmit and Receive 512- to 1023-Byte Frame Register Definition ................................ 14-63

14-54

Transmit and Receive 1024- to 1518-Byte Frame Register Definition .............................. 14-63

14-55

Transmit and Receive 1519- to 1522-Byte VLAN Frame Register Definition .................. 14-64

14-56

Receive Byte Counter Register Definition.......................................................................... 14-64

14-57

Receive Packet Counter Register Definition ...................................................................... 14-65

14-58

Receive FCS Error Counter Register Definition................................................................. 14-65

14-59

Receive Multicast Packet Counter Register Definition ...................................................... 14-66

14-60

Receive Broadcast Packet Counter Register Definition ..................................................... 14-66

14-61

Receive Control Frame Packet Counter Register Definition .............................................. 14-67

14-62

Receive Pause Frame Packet Counter Register Definition ................................................. 14-67

14-63

Receive Unknown Opcode Packet Counter Register Definition ........................................ 14-68

14-64

Receive Alignment Error Counter Register Definition....................................................... 14-68

14-65

Receive Frame Length Error Counter Register Definition ................................................. 14-69

14-66

Receive Code Error Counter Register Definition ............................................................... 14-69

14-67

Receive Carrier Sense Error Counter Register Definition .................................................. 14-70

14-68

Receive Undersize Packet Counter Register Definition ..................................................... 14-70

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