MPC8540 datasheet(10/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

6.3.1

General-Purpose Registers (GPRs).............................................................................. 6-8

6.3.2

Integer Exception Register (XER)............................................................................... 6-8

6.4

Registers for Branch Operations...................................................................................... 6-9

6.4.1

Condition Register (CR) .............................................................................................. 6-9

6.4.2

Link Register (LR)..................................................................................................... 6-11

6.4.3

Count Register (CTR)................................................................................................ 6-11

6.5

Processor Control Registers ........................................................................................... 6-11

6.5.1

Machine State Register (MSR) .................................................................................. 6-12

6.5.2

Processor ID Register (PIR) ...................................................................................... 6-14

6.5.3

Processor Version Register (PVR)............................................................................. 6-14

6.5.4

System Version Register (SVR)................................................................................. 6-14

6.6

Timer Registers ..............................................................................................................6-15

6.6.1

Timer Control Register (TCR)................................................................................... 6-15

6.6.2

Timer Status Register (TSR)...................................................................................... 6-16

6.6.3

Time Base Registers .................................................................................................. 6-17

6.6.4

Decrementer Register ................................................................................................ 6-17

6.6.5

Decrementer Auto-Reload Register (DECAR).......................................................... 6-17

6.7

Interrupt Registers..........................................................................................................6-18

6.7.1

Interrupt Registers Defined by Book E...................................................................... 6-18

6.7.1.1

Save/Restore Register 0 (SRR0)............................................................................ 6-18

6.7.1.2

Save/Restore Register 1 (SRR1)............................................................................ 6-18

6.7.1.3

Critical Save/Restore Register 0 (CSRR0) ............................................................ 6-18

6.7.1.4

Critical Save/Restore Register 1 (CSRR1) ............................................................ 6-19

6.7.1.5

Data Exception Address Register (DEAR)............................................................ 6-19

6.7.1.6

Interrupt Vector Prefix Register (IVPR) ................................................................ 6-19

6.7.1.7

Interrupt Vector Offset Registers (IVORn)............................................................ 6-19

6.7.1.8

Exception Syndrome Register (ESR) .................................................................... 6-20

6.7.2

EIS-Defined Interrupt Registers ................................................................................ 6-21

6.7.2.1

Machine Check Save/Restore Register 0 (MCSRR0) ........................................... 6-21

6.7.2.2

Machine Check Save/Restore Register 1 (MCSRR1) ........................................... 6-22

6.7.2.3

Machine Check Address Register (MCAR) .......................................................... 6-22

6.7.2.4

Machine Check Syndrome Register (MCSR)........................................................ 6-23

6.8

Software-Use SPRs (SPRG0–SPRG7 and USPRG0) ................................................... 6-24

6.9

Branch Target Buffer (BTB) Registers .......................................................................... 6-25

6.9.1

Branch Buffer Entry Address Register (BBEAR) ..................................................... 6-25

6.9.2

Branch Buffer Target Address Register (BBTAR) .................................................... 6-25

6.9.3

Branch Unit Control and Status Register (BUCSR).................................................. 6-26

6.10

Hardware Implementation-Dependent Registers ........................................................... 6-27

6.10.1

Hardware Implementation-Dependent Register 0 (HID0)......................................... 6-27

6.10.2

Hardware Implementation-Dependent Register 1 (HID1)......................................... 6-28

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