MPC8540 datasheet(141/1302 Pages) FREESCALE

141 / 1302 page

Complete CCSR Map

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

2-23

0x0_8C90

POWAR4—PCI/X outbound window 4 attributes

R/W

0x0000_0000

16.3.1.2.4/16-22

0x0_8C94–

0x0_8D9C

Reserved

—

0x0_8DA0–0x0_8DBC–Inbound Window 3

0x0_8DA0

PITAR3—PCI/X inbound window 3 translation

address register

R/W

0x0000_0000

16.3.1.3.1/16-25

0x0_8DA4

Reserved

—

0x0_8DA8

PIWBAR3—PCI/X inbound window 3 base address

R/W

0x0000_0000

16.3.1.3.2/16-25

0x0_8DAC

PIWBEAR3—PCI/X inbound window 3 base

extended address register

R/W

0x0000_0000

16.3.1.3.3/16-26

0x0_8DB0

PIWAR3—PCI/X inbound window 3 attributes register

R/W

0x0000_0000

16.3.1.3.4/16-26

0x0_8DB4–

0x0_8DBC

Reserved

—

0x0_8DC0–0x0_8DDC–Inbound Window 2

0x0_8DC0

PITAR2—PCI/X inbound window 2 translation

address register

R/W

0x0000_0000

16.3.1.3.1/16-25

0x0_8DC4

Reserved

—

0x0_8DC8

PIWBAR2—PCI/X inbound window 2 base address

R/W

0x0000_0000

16.3.1.3.2/16-25

0x0_8DCC

PIWBEAR2—PCI/X inbound window 2 base

extended address register

R/W

0x0000_0000

16.3.1.3.3/16-26

0x0_8DD0

PIWAR2—PCI/X inbound window 2 attributes register

R/W

0x0000_0000

16.3.1.3.4/16-26

0x0_8DD4–

0x0_8DDC

Reserved

—

0x0_8DE0–0x0_8DFC–Inbound Window 1

0x0_8DE0

PITAR1—PCI/X inbound window 1 translation

address register

R/W

0x0000_0000

16.3.1.3.1/16-25

0x0_8DE4

Reserved

—

0x0_8DE8

PIWBAR1—PCI/X inbound window 1 base address

R/W

0x0000_0000

16.3.1.3.2/16-25

0x0_8DEC

Reserved

—

0x0_8DF0

PIWAR1—PCI/X inbound window 1 attributes register

R/W

0x0000_0000

16.3.1.3.4/16-26

0x0_8DF4–

0x0_8DFC

Reserved

—

Table 2-9. Memory Map (continued)

Offset

Access

Reset

Section/Page

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