MPC8540 datasheet(69/1302 Pages) FREESCALE

69 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

lxix

Tables

Table

Number

Title

Page

Number

13-5

Memory Bank Sizes in Relation to Address Mask ............................................................. 13-13

13-6

ORn—GPCM Field Descriptions ....................................................................................... 13-14

13-7

ORn—UPM Field Descriptions .......................................................................................... 13-16

13-8

ORn—SDRAM Field Descriptions .................................................................................... 13-18

13-9

MAR Field Description....................................................................................................... 13-19

13-10

MxMR Field Descriptions................................................................................................... 13-19

13-11

MRTPR Field Descriptions ................................................................................................. 13-22

13-12

MDR Field Description....................................................................................................... 13-22

13-13

LSDMR Field Descriptions ................................................................................................ 13-23

13-14

LURT Field Descriptions .................................................................................................... 13-25

13-15

LSRT Field Descriptions..................................................................................................... 13-25

13-16

LTESR Field Descriptions .................................................................................................. 13-26

13-17

LTEDR Field Descriptions.................................................................................................. 13-27

13-18

LTEIR Field Descriptions ................................................................................................... 13-29

13-19

LTEATR Field Descriptions................................................................................................ 13-30

13-20

LTEAR Field Descriptions.................................................................................................. 13-30

13-21

LBCR Field Descriptions.................................................................................................... 13-31

13-22

LCRR Field Descriptions.................................................................................................... 13-32

13-23

GPCM Write Control Signal Timing for LCRR[CLKDIV] = 4 or 8.................................. 13-40

13-24

GPCM Read Control Signal Timing for LCRR[CLKDIV] = 4 or 8................................... 13-41

13-25

GPCM Write Control Signal Timing for LCRR[CLKDIV] = 2 ......................................... 13-42

13-26

GPCM Read Control Signal Timing for LCRR[CLKDIV] = 2 .......................................... 13-43

13-27

Boot Bank Field Values after Reset .................................................................................... 13-51

13-28

SDRAM Interface Commands ............................................................................................ 13-53

13-29

UPM Routines Start Addresses........................................................................................... 13-64

13-30

RAM Word Field Descriptions ........................................................................................... 13-69

13-31

MxMR Loop Field Use ....................................................................................................... 13-74

13-32

UPM Address Multiplexing ................................................................................................ 13-75

13-33

Data Bus Requirements For Read Cycle............................................................................. 13-89

13-34

Micron SDRAM Devices.................................................................................................... 13-91

13-35

LADn Signal Connections to 128-Mbyte SDRAM ............................................................ 13-93

13-36

Logical Address Bus Partitioning ....................................................................................... 13-94

13-37

SDRAM Device Address Port during Address Phase ........................................................ 13-94

13-38

SDRAM Device Address Port during READ/WRITE Command...................................... 13-94

13-39

13-40

Logical Address Partitioning .............................................................................................. 13-96

13-41

SDRAM Device Address Port During Address Phase........................................................ 13-96

13-42

SDRAM Device Address Port During READ/WRITE Command..................................... 13-96

13-43

13-44

SDRAM Capacitance .......................................................................................................... 13-99

MPC8540 датащи(PDF) 69 Page - Freescale Semiconductor, Inc

MPC8540 датащи(HTML) 69 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL