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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 146 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 146 Page - Freescale Semiconductor, Inc |
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146 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 2-28 Freescale Semiconductor Memory Map 0x2_4000– 0x2_400C Reserved R 0x0000_0000 — 0x2_4010 IEVENT—Interrupt event register R/W 0x0000_0000 14.5.3.1.1/14-20 0x2_4014 IMASK—Interrupt mask register R/W 0x0000_0000 14.5.3.1.2/14-23 0x2_4018 EDIS—Error disabled register R/W 0x0000_0000 14.5.3.1.3/14-24 0x2_401C Reserved R 0x0000_0000 — 0x2_4020 ECNTRL—Ethernet control register R/W 0x0000_0000 14.5.3.1.4/14-25 0x2_4024 MINFLR—Minimum frame length register R/W 0x0000_0040 14.5.3.1.5/14-26 0x2_4028 PTV—Pause time value register R/W 0x0000_0000 14.5.3.1.6/14-27 0x2_402C DMACTRL—DMA control register R/W 0x0000_0000 14.5.3.1.7/14-28 0x2_4030 TBIPA—TBI PHY address register R/W 0x0000_0000 14.5.3.1.8/14-29 0x2_4034– 0x2_4088 Reserved R 0x0000_0000 — TSEC1 FIFO Control and Status Registers 0x2_404C FIFO_PAUSE_CTRL—FIFO pause control register R/W 0x0000_0000 14.5.3.2.1/14-30 0x2_4050– 0x2_4088 Reserved R 0x0000_0000 — 0x2_408C FIFO_TX_THR—FIFO transmit threshold register R/W 0x0000_0100 14.5.3.2.2/14-31 0x2_4090– 0x2_4094 Reserved R 0x0000_0000 — 0x2_4098 FIFO_TX_STARVE—FIFO transmit starve register R/W 0x0000_0080 14.5.3.2.3/14-32 0x2_409C FIFO_TX_STARVE_SHUTOFF—FIFO transmit starve shutoff register R/W 0x0000_0100 14.5.3.2.4/14-32 0x2_40A0– 0x2_40FC Reserved R 0x0000_0000 — TSEC1 Transmit Control and Status Registers 0x2_4100 TCTRL—Transmit control register R/W 0x0000_0000 14.5.3.3.1/14-33 0x2_4104 TSTAT—Transmit status register R/W 0x0000_0000 14.5.3.3.2/14-34 0x2_4108 Reserved R 0x0000_0000 — 0x2_410C TBDLEN—TxBD data length register R 0x0000_0000 14.5.3.3.3/14-35 0x2_4110 TXIC—Transmit interrupt coalescing configuration register R/W 0x0000_0000 14.5.3.3.4/14-35 0x2_4114– 0x2_4120 Reserved R 0x0000_0000 — 0x2_4124 CTBPTR—Current TxBD pointer register R 0x0000_0000 14.5.3.3.5/14-36 0x2_4128– 0x2_4180 Reserved R 0x0000_0000 — 0x2_4184 TBPTR—TxBD pointer register R/W 0x0000_0000 14.5.3.3.6/14-37 Table 2-9. Memory Map (continued) Offset Register Access Reset Section/Page |
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