MPC8540 datasheet(23/1302 Pages) FREESCALE

23 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xxiii

Contents

Paragraph

Number

Title

Page

Number

14.5.3.1.1

Interrupt Event Register (IEVENT) ................................................................ 14-20

14.5.3.1.2

Interrupt Mask Register (IMASK) .................................................................. 14-23

14.5.3.1.3

Error Disabled Register (EDIS)....................................................................... 14-24

14.5.3.1.4

Ethernet Control Register (ECNTRL) ............................................................. 14-25

14.5.3.1.5

Minimum Frame Length Register (MINFLR)................................................. 14-26

14.5.3.1.6

Pause Time Value Register (PTV) ................................................................... 14-27

14.5.3.1.7

DMA Control Register (DMACTRL) ............................................................. 14-28

14.5.3.1.8

TBI Physical Address Register (TBIPA) ......................................................... 14-29

14.5.3.2

TSEC FIFO Control and Status Registers ........................................................... 14-30

14.5.3.2.1

FIFO Pause Control Register (FIFO_PAUSE_CTRL) ................................... 14-30

14.5.3.2.2

FIFO Transmit Threshold Register (FIFO_TX_THR) .................................... 14-31

14.5.3.2.3

FIFO Transmit Starve Register (FIFO_TX_STARVE) ................................... 14-32

14.5.3.2.4

FIFO Transmit Starve Shutoff Register

(FIFO_TX_STARVE_SHUTOFF).............................................................. 14-32

14.5.3.3

TSEC Transmit Control and Status Registers...................................................... 14-33

14.5.3.3.1

Transmit Control Register (TCTRL) ............................................................... 14-33

14.5.3.3.2

Transmit Status Register (TSTAT) .................................................................. 14-34

14.5.3.3.3

TxBD Data Length Register (TBDLEN)......................................................... 14-35

14.5.3.3.4

Transmit Interrupt Coalescing Configuration Register (TXIC) ...................... 14-35

14.5.3.3.5

Current Transmit Buffer Descriptor Pointer Register (CTBPTR) ................... 14-36

14.5.3.3.6

Transmit Buffer Descriptor Pointer Register (TBPTR) ................................... 14-37

14.5.3.3.7

Transmit Descriptor Base Address Register (TBASE) ................................... 14-37

14.5.3.3.8

Out-of-Sequence TxBD Register (OSTBD).................................................... 14-38

14.5.3.3.9

Out-of-Sequence Tx Data Buffer Pointer Register (OSTBDP)....................... 14-40

14.5.3.4

TSEC Receive Control and Status Registers ....................................................... 14-40

14.5.3.4.1

Receive Control Register (RCTRL) ................................................................ 14-41

14.5.3.4.2

Receive Status Register (RSTAT).................................................................... 14-41

14.5.3.4.3

RxBD Data Length Register (RBDLEN) ........................................................ 14-42

14.5.3.4.4

Receive Interrupt Coalescing Configuration Register (RXIC)........................ 14-43

14.5.3.4.5

Current Receive Buffer Descriptor Pointer Register (CRBPTR) .................... 14-44

14.5.3.4.6

Maximum Receive Buffer Length Register (MRBLR) ................................... 14-44

14.5.3.4.7

Receive Buffer Descriptor Pointer Register (RBPTR) .................................... 14-45

14.5.3.4.8

Receive Descriptor Base Address Register (RBASE)..................................... 14-45

14.5.3.5

MAC Functionality.............................................................................................. 14-46

14.5.3.5.1

Configuring the MAC...................................................................................... 14-46

14.5.3.5.2

Controlling CSMA/CD.................................................................................... 14-46

14.5.3.5.3

Handling Packet Collisions ............................................................................. 14-47

14.5.3.5.4

Controlling Packet Flow .................................................................................. 14-47

14.5.3.5.5

Controlling PHY Links.................................................................................... 14-48

14.5.3.6

MAC Registers .................................................................................................... 14-49

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