MPC8540 datasheet(43/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xliii

Figures

Figure

Number

Title

Page

Number

Figures

1-1

MPC8540 Block Diagram....................................................................................................... 1-2

1-2

Processing Transactions Across the On-Chip Fabric............................................................ 1-21

1-3

High-Performance Communication System Using SMP...................................................... 1-22

1-4

High-Performance Communication System Using MPC8540 ............................................. 1-22

1-5

RAID Controller Application Using MPC8540.................................................................... 1-23

1-6

VPN Access Point Enabled by RapidIO and Ethernet.......................................................... 1-23

1-7

MPC8540 with SERDES ...................................................................................................... 1-24

1-8

MPC8540 with a DSP Farm Enabled by General-Purpose Chip Select

Machine or User Programmable Machine on the Local Bus Controller Port .................. 1-24

2-1

Local Memory Map Example ................................................................................................. 2-2

2-2

Local Access Window n Base Address Registers (LAWBAR0–LAWBAR7) ....................... 2-6

2-3

Local Access Window n Attributes Registers (LAWAR0–LAWAR7) ................................... 2-6

2-4

Top-Level Register Map Example ........................................................................................ 2-10

2-5

General Utilities Registers Mapping to Configuration, Control, and Status

Memory Block.................................................................................................................. 2-13

2-6

PIC Mapping to Configuration, Control, and Status Memory Block ................................... 2-14

2-7

RapidIO Mapping to Configuration, Control, and Status Memory Block............................ 2-15

2-8

Device-Specific Register Mapping to Configuration, Control, and Status

Memory Block.................................................................................................................. 2-16

3-1

MPC8540 Signal Groupings ................................................................................................... 3-3

4-1

Configuration, Control, and Status Register Base Address Register (CCSRBAR)................ 4-5

4-2

Alternate Configuration Base Address Register (ALTCBAR) ............................................... 4-6

4-3

Alternate Configuration Attribute Register (ALTCAR) ......................................................... 4-6

4-4

Boot Page Translation Register (BPTR) ................................................................................. 4-8

4-5

Power-On Reset Sequence .................................................................................................... 4-11

4-6

Clock Subsystem Block Diagram ......................................................................................... 4-24

4-7

RapidIO Transmit Clock Options ......................................................................................... 4-24

4-8

RTC and Core Timer Facilities Clocking Options ................................................................ 4-26

5-1

e500 Core Complex Block Diagram ....................................................................................... 5-2

5-2

Four-Stage MU Pipeline, Showing Divide Bypass................................................................. 5-8

5-3

Three-Stage Load/Store Unit ..................................................................................................5-9

5-4

Instruction Pipeline Flow ...................................................................................................... 5-15

5-5

GPR Issue Queue (GIQ) ....................................................................................................... 5-17

5-6

e500 Core Programming Model............................................................................................ 5-19

5-7

MMU Structure ..................................................................................................................... 5-25

5-8

Effective-to-Real Address Translation Flow......................................................................... 5-26

6-1

Core Register Model ............................................................................................................... 6-2

6-2

Integer Exception Register (XER) .......................................................................................... 6-8

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