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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 144 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 144 Page - Freescale Semiconductor, Inc |
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144 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 2-26 Freescale Semiconductor Memory Map 0x2_1148 – 0x2_117C Reserved — — — 0x2_1180 MRn—DMA 1 mode register R/W 0x0000_0000 15.3.2.1/15-10 0x2_1184 SRn—DMA 1 status register Special 0x0000_0000 15.3.2.2/15-13 0x2_1188 Reserved — — — 0x2_118C CLNDARn—DMA 1 current link descriptor address register R/W 0x0000_0000 15.3.2.3/15-14 0x2_1190 SATRn—DMA 1 source attributes register R/W 0x0000_0000 15.3.2.4/15-16 0x2_1194 SARn—DMA 1 source address register R/W 0x0000_0000 15.3.2.5/15-18 0x2_1198 DATRn—DMA 1 destination attributes register R/W 0x0000_0000 15.3.2.6/15-19 0x2_119C DARn—DMA 1 destination address register R/W 0x0000_0000 15.3.2.7/15-21 0x2_11A0 BCRn—DMA 1 byte count register R/W 0x0000_0000 15.3.2.8/15-23 0x2_11A4 Reserved — — — 0x2_11A8 NLNDARn—DMA 1 next link descriptor address register R/W 0x0000_0000 15.3.2.9/15-23 0x2_11AC – 0x2_11B0 Reserved — — — 0x2_11B4 CLSDARn—DMA 1 current list alternate base descriptor address register R/W 0x0000_0000 15.3.2.10/15-24 0x2_11B8 Reserved — — — 0x2_11BC NLSDARn—DMA 1 next list descriptor address register R/W 0x0000_0000 15.3.2.11/15-25 0x2_11C0 SSRn—DMA 1 source stride register R/W 0x0000_0000 15.3.2.12/15-25 0x2_11C4 DSRn—DMA 1 destination stride register R/W 0x0000_0000 15.3.2.13/15-26 0x2_11C8 – 0x2_11FC Reserved — — — 0x2_1200 MRn—DMA 2 mode register R/W 0x0000_0000 15.3.2.1/15-10 0x2_1204 SRn—DMA 2 status register Special 0x0000_0000 15.3.2.2/15-13 0x2_1208 Reserved — — — 0x2_120C CLNDARn—DMA 2 current link descriptor address register R/W 0x0000_0000 15.3.2.3/15-14 0x2_1210 SATRn—DMA 2 source attributes register R/W 0x0000_0000 15.3.2.4/15-16 0x2_1214 SARn—DMA 2 source address register R/W 0x0000_0000 15.3.2.5/15-18 0x2_1218 DATRn—DMA 2 destination attributes register R/W 0x0000_0000 15.3.2.6/15-19 0x2_121C DARn—DMA 2 destination address register R/W 0x0000_0000 15.3.2.7/15-21 0x2_1220 BCRn—DMA 2 byte count register R/W 0x0000_0000 15.3.2.8/15-23 0x2_1224 Reserved — — — Table 2-9. Memory Map (continued) Offset Register Access Reset Section/Page |
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