MPC8540 datasheet(48/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

xlviii

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

10-33

Processor Current Task Priority Register (CTPR) .............................................................. 10-40

10-34

Processor Who Am I Register (WHOAMI)........................................................................ 10-41

10-35

Processor Interrupt Acknowledge Register (IACK) ........................................................... 10-42

10-36

End of Interrupt Register (EOI) .......................................................................................... 10-42

10-37

PIC Interrupt Processing Flow Diagram ............................................................................. 10-44

11-1

I2C Block Diagram................................................................................................................ 11-1

11-2

I2C Address Register (I2CADR)........................................................................................... 11-5

11-3

I2C Frequency Divider Register (I2CFDR) .......................................................................... 11-5

11-4

I2C Control Register (I2CCR)............................................................................................... 11-6

11-5

I2C Status Register (I2CSR) ................................................................................................. 11-8

11-6

I2C Data Register (I2CDR) ................................................................................................... 11-9

11-7

I2C Digital Filter Sampling Rate Register (I2CDFSRR).................................................... 11-10

11-8

I2C Interface Transaction Protocol.......................................................................................11-11

11-9

EEPROM Data Format for One Register Preload Command............................................. 11-19

11-10

EEPROM Contents ............................................................................................................. 11-19

11-11

Example I2C Interrupt Service Routine Flowchart ............................................................. 11-24

12-1

UART Block Diagram .......................................................................................................... 12-2

12-2

Receiver Buffer Registers (URBR0, URBR1)...................................................................... 12-6

12-3

Transmitter Holding Registers (UTHR0, UTHR1)............................................................... 12-7

12-4

Divisor Most Significant Byte Registers (UDMB0, UDMB1)............................................. 12-7

12-5

Divisor Least Significant Byte Registers (UDLB0, UDLB1)............................................... 12-8

12-6

Interrupt Enable Register (UIER) ......................................................................................... 12-9

12-7

Interrupt ID Registers (UIIR).............................................................................................. 12-10

12-8

FIFO Control Registers (UFCR0, UFCR1) ........................................................................ 12-11

12-9

Line Control Register (ULCR) ........................................................................................... 12-13

12-10

Modem Control Register (UMCR) ..................................................................................... 12-14

12-11

Line Status Register (ULSR) .............................................................................................. 12-15

12-12

Modem Status Register (UMSR) ........................................................................................ 12-16

12-13

Scratch Register (USCR) .................................................................................................... 12-17

12-14

Alternate Function Register (UAFR) .................................................................................. 12-18

12-15

DMA Status Register (UDSR)............................................................................................ 12-18

12-16

UART Bus Interface Transaction Protocol Example .......................................................... 12-21

13-1

Local Bus Controller Block Diagram ................................................................................... 13-1

13-2

Base Registers (BRn) .......................................................................................................... 13-11

13-3

Option Registers (ORn) in GPCM Mode............................................................................ 13-14

13-4

Option Registers (ORn) in UPM Mode .............................................................................. 13-16

13-5

Option Registers (ORn) in SDRAM Mode......................................................................... 13-17

13-6

UPM Memory Address Register (MAR) ............................................................................ 13-18

13-7

UPM Mode Registers (MxMR)........................................................................................... 13-19

13-8

Memory Refresh Timer Prescaler Register (MRTPR)........................................................ 13-21

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