MPC8540 datasheet(145/1302 Pages) FREESCALE

145 / 1302 page

Complete CCSR Map

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

2-27

0x2_1228

NLNDARn—DMA 2 next link descriptor address

R/W

0x0000_0000

15.3.2.9/15-23

0x2_122C

–

0x2_1230

Reserved

—

0x2_1234

CLSDARn—DMA 2 current list alternate base

descriptor address register

R/W

0x0000_0000

15.3.2.10/15-24

0x2_1238

Reserved

—

0x2_123C

NLSDARn—DMA 2 next list descriptor address

R/W

0x0000_0000

15.3.2.11/15-25

0x2_1240

SSRn—DMA 2 source stride register

R/W

0x0000_0000

15.3.2.12/15-25

0x2_1244

DSRn—DMA 2 destination stride register

R/W

0x0000_0000

15.3.2.13/15-26

0x2_1248

–

0x2_127C

Reserved

—

0x2_1280

MRn—DMA 3 mode register

R/W

0x0000_0000

15.3.2.1/15-10

0x2_1284

SRn—DMA 3 status register

Special

0x0000_0000

15.3.2.2/15-13

0x2_1288

Reserved

—

0x2_128C

CLNDARn—DMA 3 current link descriptor address

R/W

0x0000_0000

15.3.2.3/15-14

0x2_1290

SATRn—DMA 3 source attributes register

R/W

0x0000_0000

15.3.2.4/15-16

0x2_1294

SARn—DMA 3 source address register

R/W

0x0000_0000

15.3.2.5/15-18

0x2_1298

DATRn—DMA 3 destination attributes register

R/W

0x0000_0000

15.3.2.6/15-19

0x2_129C

DARn—DMA 3 destination address register

R/W

0x0000_0000

15.3.2.7/15-21

0x2_12A0

BCRn—DMA 3 byte count register

R/W

0x0000_0000

15.3.2.8/15-23

0x2_12A4

Reserved

—

0x2_12A8

NLNDARn—DMA 3 next link descriptor address

R/W

0x0000_0000

15.3.2.9/15-23

0x2_12AC

–

0x2_12B0

Reserved

—

0x2_12B4

CLSDARn—DMA 3 current list alternate base

descriptor address register

R/W

0x0000_0000

15.3.2.10/15-24

0x2_12B8

Reserved

—

0x2_12BC

NLSDARn—DMA 3 next list descriptor address

R/W

0x0000_0000

15.3.2.11/15-25

0x2_12C0

SSRn—DMA 3 source stride register

R/W

0x0000_0000

15.3.2.12/15-25

0x2_12C4

DSRn—DMA 3 destination stride register

R/W

0x0000_0000

15.3.2.13/15-26

0x2_12C8

–

0x2_12FC

Reserved

—

0x2_1300

DGSR—DMA general status register

Read

0x0000_0000

15.3.2.14/15-26

TSEC1 General Control and Status Registers

Table 2-9. Memory Map (continued)

Offset

Access

Reset

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