MPC8540 datasheet(25/1302 Pages) FREESCALE

25 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xxv

Contents

Paragraph

Number

Title

Page

Number

14.5.3.7.20

Receive Undersize Packet Counter Register (RUND) .................................... 14-70

14.5.3.7.21

Receive Oversize Packet Counter Register (ROVR) ...................................... 14-71

14.5.3.7.22

Receive Fragments Counter Register (RFRG) ................................................ 14-71

14.5.3.7.23

Receive Jabber Counter Register (RJBR) ....................................................... 14-72

14.5.3.7.24

Receive Dropped Packet Counter Register (RDRP) ....................................... 14-72

14.5.3.7.25

Transmit Byte Counter Register (TBYT) ........................................................ 14-73

14.5.3.7.26

Transmit Packet Counter Register (TPKT) ..................................................... 14-73

14.5.3.7.27

Transmit Multicast Packet Counter Register (TMCA).................................... 14-74

14.5.3.7.28

Transmit Broadcast Packet Counter Register (TBCA).................................... 14-74

14.5.3.7.29

Transmit Pause Control Frame Counter Register (TXPF) .............................. 14-75

14.5.3.7.30

Transmit Deferral Packet Counter Register (TDFR)....................................... 14-75

14.5.3.7.31

Transmit Excessive Deferral Packet Counter Register (TEDF) ...................... 14-76

14.5.3.7.32

Transmit Single Collision Packet Counter Register (TSCL)........................... 14-76

14.5.3.7.33

Transmit Multiple Collision Packet Counter Register (TMCL)...................... 14-77

14.5.3.7.34

Transmit Late Collision Packet Counter Register (TLCL).............................. 14-77

14.5.3.7.35

Transmit Excessive Collision Packet Counter Register (TXCL) .................... 14-78

14.5.3.7.36

Transmit Total Collision Counter Register (TNCL)........................................ 14-78

14.5.3.7.37

Transmit Drop Frame Counter Register (TDRP) ............................................ 14-79

14.5.3.7.38

Transmit Jabber Frame Counter Register (TJBR) ........................................... 14-79

14.5.3.7.39

Transmit FCS Error Counter Register (TFCS) ................................................ 14-80

14.5.3.7.40

Transmit Control Frame Counter Register (TXCF) ........................................ 14-80

14.5.3.7.41

Transmit Oversize Frame Counter Register (TOVR)...................................... 14-81

14.5.3.7.42

Transmit Undersize Frame Counter Register (TUND) ................................... 14-81

14.5.3.7.43

Transmit Fragment Counter Register (TFRG) ................................................ 14-82

14.5.3.7.44

Carry Register 1 (CAR1) ................................................................................. 14-82

14.5.3.7.45

Carry Register 2 (CAR2) ................................................................................. 14-84

14.5.3.7.46

Carry Mask Register 1 (CAM1) ...................................................................... 14-85

14.5.3.7.47

Carry Mask Register 2 (CAM2) ...................................................................... 14-86

14.5.3.8

Hash Function Registers ...................................................................................... 14-87

14.5.3.8.1

Individual Address Registers 0–7 (IADDRn) ................................................. 14-88

14.5.3.8.2

Group Address Registers 0–7 (GADDRn) ...................................................... 14-88

14.5.3.9

Attribute Registers ............................................................................................... 14-89

14.5.3.9.1

Attribute Register (ATTR)............................................................................... 14-89

14.5.3.9.2

Attribute Extract Length and Extract Index Register (ATTRELI) .................. 14-90

14.5.4

Ten-Bit Interface (TBI) ............................................................................................ 14-91

14.5.4.1

TBI MII Set Register Descriptions ...................................................................... 14-91

14.5.4.2

Control Register (CR).......................................................................................... 14-92

14.5.4.3

Status Register (SR) ........................................................................................... 14-93

14.5.4.4

AN Advertisement Register (ANA) .................................................................... 14-94

14.5.4.5

AN Link Partner Base Page Ability Register (ANLPBPA)................................. 14-96

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