MPC8540 datasheet(46/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

xlvi

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

7-19

L2 Error Interrupt Enable Register (L2ERRINTEN) ........................................................... 7-18

7-20

L2 Error Attributes Capture Register (L2ERRATTR) .......................................................... 7-19

7-21

L2 Error Address Capture Register (L2ERRADDR) ........................................................... 7-20

7-22

L2 Error Control Register (L2ERRCTL).............................................................................. 7-20

7-23

L2 Cache Line Replacement Algorithm ............................................................................... 7-28

8-1

e500 Coherency Module Block Diagram................................................................................ 8-1

8-2

ECM CCB Address Configuration Register (EEBACR)........................................................ 8-3

8-3

ECM CCB Port Configuration Register (EEBPCR)............................................................... 8-4

8-4

ECM Error Detect Register (EEDR)....................................................................................... 8-5

8-5

ECM Error Enable Register (EEER) ...................................................................................... 8-6

8-6

ECM Error Attributes Capture Register (EEATR) ................................................................. 8-7

8-7

ECM Error Address Capture Register (EEADR) ................................................................... 8-8

9-1

DDR Memory Controller Simplified Block Diagram............................................................. 9-2

9-2

Chip Select Bounds Registers (CSn_BNDS)........................................................................ 9-10

9-3

Chip Select Configuration Register (CSn_CONFIG) ........................................................... 9-10

9-4

DDR SDRAM Timing Configuration Register 1 (TIMING_CFG_1).................................. 9-11

9-5

DDR SDRAM Timing Configuration Register 2 (TIMING_CFG_2).................................. 9-13

9-6

DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) .............................. 9-14

9-7

DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)............................. 9-16

9-8

DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL) .................. 9-16

9-9

Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI) ......... 9-17

9-10

Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)......... 9-18

9-11

Memory Data Path Error Injection Mask ECC Register (ECC_ERR_INJECT) .................. 9-18

9-12

Memory Data Path Read Capture High Register (CAPTURE_DATA_HI).......................... 9-19

9-13

Memory Data Path Read Capture Low Register (CAPTURE_DATA_LO) ......................... 9-20

9-14

Memory Data Path Read Capture ECC Register (CAPTURE_ECC)................................... 9-20

9-15

Memory Error Detect Register (ERR_DETECT) ................................................................. 9-21

9-16

Memory Error Disable Register (ERR_DISABLE).............................................................. 9-22

9-17

Memory Error Interrupt Enable Register (ERR_INT_EN)................................................... 9-22

9-18

Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)........................... 9-23

9-19

Memory Error Address Capture Register (CAPTURE_ADDRESS) ................................... 9-24

9-20

Single-Bit ECC Memory Error Management Register (ERR_SBE) .................................... 9-25

9-21

DDR Memory Controller Block Diagram ............................................................................ 9-26

9-22

Controller DLL Timing Loop ............................................................................................... 9-27

9-23

Typical Dual Data Rate SDRAM Internal Organization....................................................... 9-28

9-24

Typical DDR SDRAM Interface Signals .............................................................................. 9-28

9-25

Example 256-Mbyte DDR SDRAM Configuration with ECC............................................. 9-29

9-26

DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 9-36

9-27

DDR SDRAM Single-Beat (Double-Word) Write Timing—ACTTORW = 3 ..................... 9-37

9-28

DDR SDRAM Burst Write Timing—ACTTORW = 4 ......................................................... 9-37

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