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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 37 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 37 Page - Freescale Semiconductor, Inc |
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37 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor xxxvii Contents Paragraph Number Title Page Number 18.4.1.6 General-Purpose POR Configuration Register (GPPORCR) ................................ 18-9 18.4.1.7 General-Purpose I/O Control Register (GPIOCR) .............................................. 18-10 18.4.1.8 General-Purpose Output Data Register (GPOUTDR) ......................................... 18-11 18.4.1.9 General-Purpose Input Data Register (GPINDR)................................................ 18-12 18.4.1.10 Alternate Function Signal Multiplex Control Register (PMUXCR) ................... 18-12 18.4.1.11 Device Disable Register (DEVDISR) ................................................................. 18-13 18.4.1.12 Power Management Control and Status Register (POWMGTCSR) ................... 18-15 18.4.1.13 Machine Check Summary Register (MCPSUMR).............................................. 18-16 18.4.1.14 Processor Version Register (PVR)....................................................................... 18-17 18.4.1.15 System Version Register (SVR)........................................................................... 18-18 18.4.1.16 Clock Out Control Register (CLKOCR) ............................................................. 18-18 18.4.1.17 DDR DLL Control Register (DDRDLLCR) ....................................................... 18-19 18.4.1.18 Local Bus DLL Control Register (LBDLLCR)................................................... 18-20 18.5 Functional Description................................................................................................. 18-21 18.5.1 Power Management ................................................................................................. 18-21 18.5.1.1 Relationship Between Core and Device Power Management States................... 18-21 18.5.1.2 CKSTP_IN Is Not Power Management............................................................... 18-22 18.5.1.3 Dynamic Power Management.............................................................................. 18-22 18.5.1.4 Shutting Down Unused Blocks............................................................................ 18-22 18.5.1.5 Software-Controlled Power-Down States............................................................ 18-23 18.5.1.5.1 Doze Mode ...................................................................................................... 18-23 18.5.1.5.2 Nap Mode ........................................................................................................ 18-23 18.5.1.5.3 Sleep Mode ...................................................................................................... 18-24 18.5.1.6 Power Management Control Fields ..................................................................... 18-24 18.5.1.7 Power-Down Sequence Coordination.................................................................. 18-24 18.5.1.8 Interrupts and Power Management ...................................................................... 18-27 18.5.1.8.1 Interrupts and Power Management Controlled by MSR[WE] ........................ 18-27 18.5.1.8.2 Interrupts and Power Management Controlled by POWMGTCSR ................ 18-27 18.5.1.9 Snooping in Power-Down Modes........................................................................ 18-28 18.5.1.10 Software Considerations for Power Management ............................................... 18-28 18.5.1.11 Requirements for Reaching and Recovering from Sleep State ........................... 18-28 18.5.2 General-Purpose I/O Signals ................................................................................... 18-29 18.5.3 Interrupt and Local Bus Signal Multiplexing .......................................................... 18-29 Chapter 19 Performance Monitor 19.1 Introduction.................................................................................................................... 19-1 19.1.1 Overview.................................................................................................................... 19-1 19.1.2 Features ...................................................................................................................... 19-3 |
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