MPC8540 datasheet(57/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

lvii

Figures

Figure

Number

Title

Page

Number

17-3

Device Identity Capability Register (DIDCAR) ................................................................. 17-13

17-4

Device Information Capability Register (DICAR) ............................................................. 17-14

17-5

Assembly Identity Capability Register (AIDCAR) ............................................................ 17-14

17-6

Assembly Information Capability Register (AICAR) ........................................................ 17-15

17-7

Processing Element Features Capability Register (PEFCAR)............................................ 17-15

17-8

Switch Port Information Capability Register (SPICAR) .................................................... 17-17

17-9

Source Operations Capability Register (SOCAR) .............................................................. 17-17

17-10

Destination Operations Capability Register (DOCAR) ...................................................... 17-20

17-11

Mailbox Status Register (MSR).......................................................................................... 17-22

17-12

Port-Write and Doorbell Command and Status Register (PWDCSR) ................................ 17-23

17-13

Processing Element Logic Layer Control Command and Status Register

(PELLCCSR) ................................................................................................................. 17-24

17-14

Local Configuration Space Base Address 1 Command and Status

Register (LCSBA1CSR) ................................................................................................ 17-25

17-15

Base Device ID Command and Status Register (BDIDCSR)............................................. 17-25

17-16

Host Base Device ID Lock Command and Status Register (HBDIDLCSR)...................... 17-26

17-17

Component Tag Command and Status Register (CTCSR) ................................................. 17-26

17-18

8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status

Register (PMBH0CSR) .................................................................................................. 17-27

17-19

Port Link Time-Out Control Command and Status Register (PLTOCCSR)....................... 17-28

17-20

Port Response Time-Out Control Command and Status Register (PRTOCCSR) .............. 17-28

17-21

Port General Control Command and Status Register (PGCCSR)....................................... 17-29

17-22

Port Link Maintenance Request Command and Status Register (PLMREQCSR)............. 17-30

17-23

Port Link Maintenance Response Command and Status Register (PLMRESPCSR)......... 17-30

17-24

Port Local AckID Status Command and Status Register (PLASCSR)............................... 17-31

17-25

Port Error and Status Command and Status Register (PESCSR) ....................................... 17-32

17-26

Port Control Command and Status Register (PCCSR) ....................................................... 17-33

17-27

Configuration Register (CR) ............................................................................................... 17-34

17-28

Port Configuration Register (PCR) ..................................................................................... 17-35

17-29

Port Error Injection Register (PEIR)................................................................................... 17-36

17-30

RapidIO Outbound Window Translation Address Registers 0–8 for Standard

Transactions (ROWTARn) ............................................................................................. 17-37

17-31

RapidIO Outbound Window Translation Address Registers 0–8 for

Maintenance Transactions (ROWTARn) ....................................................................... 17-38

17-32

RapidIO Outbound Window Base Address Registers 1–8 (ROWBARn) .......................... 17-38

17-33

RapidIO Outbound Window Attributes Register 0 (ROWAR0) ......................................... 17-39

17-34

RapidIO Outbound Window Attributes Registers 1–8 (ROWARn) ................................... 17-39

17-35

RapidIO Inbound Window Translation Address Registers 0–4 (RIWTARn)..................... 17-41

17-36

RapidIO Inbound Window Base Address Registers 1–4 (RIWBARn)............................... 17-41

17-37

RapidIO Inbound Window Attributes Register 0 (RIWAR0) ............................................. 17-42

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