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MPC8540 датащи(PDF) 56 Page - Freescale Semiconductor, Inc

номер детали MPC8540
подробное описание детали  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 датащи(HTML) 56 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
lvi
Freescale Semiconductor
Figures
Figure
Number
Title
Page
Number
16-43
PCI Bus Capabilities Pointer Register ................................................................................ 16-47
16-44
PCI Bus Interrupt Line Register.......................................................................................... 16-47
16-45
PCI Bus Interrupt Pin Register............................................................................................ 16-48
16-46
PCI Bus Minimum Grant Register...................................................................................... 16-48
16-47
PCI Bus Maximum Latency Register ................................................................................. 16-49
16-48
PCI Bus Function Register.................................................................................................. 16-49
16-49
PCI Bus Arbiter Configuration Register ............................................................................. 16-50
16-50
PCI-X Next Capabilities ID Register.................................................................................. 16-51
16-51
PCI-X Capability Pointer Register...................................................................................... 16-51
16-52
PCI-X Command Register .................................................................................................. 16-52
16-53
PCI-X Status Register ......................................................................................................... 16-53
16-54
PCI/X Arbitration Example ................................................................................................ 16-55
16-55
PCI Single-Beat Read Transaction...................................................................................... 16-63
16-56
PCI Burst Read Transaction................................................................................................ 16-63
16-57
PCI Single-Beat Write Transaction ..................................................................................... 16-64
16-58
PCI Burst Write Transaction ............................................................................................... 16-64
16-59
PCI Target-Initiated Terminations....................................................................................... 16-67
16-60
DAC Single-Beat Read Example ........................................................................................ 16-69
16-61
DAC Burst Read Example .................................................................................................. 16-69
16-62
DAC Single-Beat Write Example ....................................................................................... 16-69
16-63
DAC Burst Write Example ................................................................................................. 16-70
16-64
64-Bit Dual Address Read Cycle ........................................................................................ 16-70
16-65
Standard PCI Configuration Header ................................................................................... 16-71
16-66
PCI Type 0 Configuration Translation ................................................................................ 16-75
16-67
PCI Parity Operation ........................................................................................................... 16-79
16-68
AD[31:0] During PCI-X Burst/DWORD Attribute Phase.................................................. 16-83
16-69
Typical PCI-X Write Transaction........................................................................................ 16-85
16-70
Burst Memory Write Transaction........................................................................................ 16-86
16-71
Memory Read Block Transaction ....................................................................................... 16-87
16-72
DWORD (4-Byte) Write Transaction ................................................................................. 16-88
16-73
DWORD (4-Byte) Read Transaction .................................................................................. 16-88
16-74
Split Response to a Read Transaction ................................................................................. 16-90
16-75
Split Response to a DWORD (4-Byte) Write Transaction.................................................. 16-90
16-76
Split Completion Transaction Address AD[31:0]............................................................... 16-91
16-77
AD[31:0] During PCI-X Split Completion Attribute Phase ............................................... 16-92
16-78
PCI-X Split Completion Message Format .......................................................................... 16-92
16-79
PCI-X Type 0 Configuration Translation............................................................................ 16-94
16-80
AD[31:0] During PCI-X Configuration Attribute Phase .................................................... 16-95
17-1
RapidIO High Level Block Diagram .................................................................................... 17-2
17-2
RapidIO Interface Signals Model ......................................................................................... 17-7



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