MPC8540 datasheet(60/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

19-11

Burstiness Counting Timing Diagram ................................................................................ 19-15

20-1

Debug and Watchpoint Monitor Block Diagram .................................................................. 20-2

20-2

Watchpoint Monitor Control Register 0 (WMCR0) ........................................................... 20-11

20-3

Watchpoint Monitor Control Register 1 (WMCR1) ........................................................... 20-13

20-4

Watchpoint Monitor Address Register (WMAR) ............................................................... 20-13

20-5

Watchpoint Monitor Address Mask Register (WMAMR).................................................. 20-14

20-6

Watchpoint Monitor Transaction Mask Register (WMTMR)............................................. 20-15

20-7

Watchpoint Monitor Status Register (WMSR) ................................................................... 20-16

20-8

Trace Buffer Control Register 0 (TBCR0).......................................................................... 20-17

20-9

Trace Buffer Control Register 1 (TBCR1).......................................................................... 20-18

20-10

Trace Buffer Address Register (TBAR).............................................................................. 20-19

20-11

Trace Buffer Address Mask Register (TBAMR) ................................................................ 20-20

20-12

Trace Buffer Transaction Mask Register (TBTMR) ........................................................... 20-20

20-13

Trace Buffer Status Register (TBSR).................................................................................. 20-21

20-14

Trace Buffer Access Control Register (TBACR) ............................................................... 20-22

20-15

Trace Buffer Read High Register (TBADHR).................................................................... 20-23

20-16

Trace Buffer Access Data Register (TBADR) .................................................................... 20-23

20-17

Programmed Context ID Register (PCIDR) ....................................................................... 20-24

20-18

Current Context ID Register (CCIDR) ............................................................................... 20-24

20-19

Trigger Out Source Register (TOSR).................................................................................. 20-25

20-20

e500 Coherency Module Dispatch (CMD) Trace Buffer Entry .......................................... 20-30

20-21

DDR Trace Buffer Entry ..................................................................................................... 20-31

20-22

PCI Trace Buffer Entry ....................................................................................................... 20-32

20-23

RapidIO Trace Buffer Entry................................................................................................ 20-32

21-1

10/100 Fast Ethernet Controller in Relation to the OSI Protocol Stack ............................... 21-1

21-2

Ethernet/IEEE 802.3 Frame Structure .................................................................................. 21-2

21-3

Ethernet/IEEE 802.3 Frame Structure With More Details.................................................... 21-4

21-4

FEC Block Diagram.............................................................................................................. 21-5

21-5

IEVENT Register Definition .............................................................................................. 21-14

21-6

IMASK Register Definition ................................................................................................ 21-17

21-7

EDIS Register Definition .................................................................................................... 21-18

21-8

MINFLR Register Definition.............................................................................................. 21-18

21-9

PTV Register Definition...................................................................................................... 21-19

21-10

DMACTRL Register Definition ......................................................................................... 21-20

21-11

FIFO_PAUSE_CTRL Register Definition.......................................................................... 21-22

21-12

FIFO_TX_THR Register Definition ................................................................................... 21-23

21-13

FIFO_TX_STARVE Register Definition ............................................................................ 21-24

21-14

FIFO_TX_STARVE_SHUTOFF Register Definition ........................................................ 21-25

21-15

TCTRL Register Definition ................................................................................................ 21-25

21-16

TSTAT Register Definition ................................................................................................. 21-26

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