MPC8540 datasheet(44/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

xliv

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

6-3

Condition Register (CR) ......................................................................................................... 6-9

6-4

Link Register (LR) ................................................................................................................ 6-11

6-5

Count Register (CTR) ........................................................................................................... 6-11

6-6

Machine State Register (MSR) ............................................................................................. 6-12

6-7

Processor ID Register (PIR)..................................................................................................6-14

6-8

Processor Version Register (PVR) ........................................................................................ 6-14

6-9

System Version Register (SVR)............................................................................................ 6-14

6-10

Timer Control Register (TCR) .............................................................................................. 6-15

6-11

Timer Status Register (TSR) .................................................................................................6-16

6-12

Time Base Upper/Lower Registers (TBU/TBL)................................................................... 6-17

6-13

Decrementer Register (DEC) ................................................................................................ 6-17

6-14

Decrementer Auto-Reload Register (DECAR)..................................................................... 6-17

6-15

Save/Restore Register 0 (SRR0) ........................................................................................... 6-18

6-16

Save/Restore Register 1 (SRR1) ........................................................................................... 6-18

6-17

Critical Save/Restore Register 0 (CSRR0) ........................................................................... 6-18

6-18

Critical Save/Restore Register 1 (CSRR1) ........................................................................... 6-19

6-19

Data Exception Address Register (DEAR) ........................................................................... 6-19

6-20

Interrupt Vector Prefix Register (IVPR) ............................................................................... 6-19

6-21

Interrupt Vector Offset Registers (IVORn) ........................................................................... 6-19

6-22

Exception Syndrome Register (ESR).................................................................................... 6-20

6-23

Machine Check Save/Restore Register 0 (MCSRR0)........................................................... 6-21

6-24

Machine Check Save/Restore Register 1 (MCSRR1)........................................................... 6-22

6-25

Machine Check Address Register (MCAR).......................................................................... 6-22

6-26

Machine Check Syndrome Register (MCSR) ....................................................................... 6-23

6-27

Software-Use SPRs (SPRG0–SPRG7 and USPRG0)........................................................... 6-24

6-28

Branch Buffer Entry Address Register (BBEAR) ................................................................ 6-25

6-29

Branch Buffer Target Address Register (BBTAR)................................................................ 6-25

6-30

Branch Unit Control and Status Register (BUCSR) ............................................................. 6-26

6-31

Hardware Implementation-Dependent Register 0 (HID0).................................................... 6-27

6-32

Hardware Implementation-Dependent Register 1 (HID1).................................................... 6-28

6-33

L1 Cache Control and Status Register 0 (L1CSR0) ............................................................. 6-30

6-34

L1 Cache Control and Status Register 1 (L1CSR1) ............................................................. 6-31

6-35

L1 Cache Configuration Register 0 (L1CFG0)..................................................................... 6-32

6-36

L1 Cache Configuration Register 1 (L1CFG1)..................................................................... 6-33

6-37

Process ID Registers (PID0–PID2)....................................................................................... 6-34

6-38

MMU Control and Status Register 0 (MMUCSR0) ............................................................. 6-34

6-39

MMU Configuration Register (MMUCFG) ......................................................................... 6-35

6-40

TLB Configuration Register 0 (TLB0CFG) ......................................................................... 6-35

6-41

TLB Configuration Register 1 (TLB1CFG) ......................................................................... 6-36

6-42

MAS Register 0 (MAS0) ...................................................................................................... 6-37

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