MPC8540 datasheet(18/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

xviii

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

11.5.3

Post-Transfer Software Response ............................................................................ 11-21

11.5.4

Generation of STOP................................................................................................. 11-22

11.5.5

Generation of Repeated START .............................................................................. 11-22

11.5.6

Generation of SCL When SDA Low ....................................................................... 11-22

11.5.7

Slave Mode Interrupt Service Routine..................................................................... 11-23

11.5.7.1

Slave Transmitter and Received Acknowledge ................................................... 11-23

11.5.7.2

Loss of Arbitration and Forcing of Slave Mode .................................................. 11-23

11.5.8

Interrupt Service Routine Flowchart........................................................................ 11-23

Chapter 12

DUART

12.1

Overview........................................................................................................................ 12-1

12.1.1

Features ...................................................................................................................... 12-2

12.1.2

Modes of Operation ................................................................................................... 12-3

12.2

External Signal Descriptions ......................................................................................... 12-3

12.2.1

Signal Overview ........................................................................................................ 12-3

12.2.2

Detailed Signal Descriptions ..................................................................................... 12-3

12.3

Memory Map/Register Definition ................................................................................. 12-4

12.3.1

Register Descriptions ................................................................................................. 12-6

12.3.1.1

Receiver Buffer Registers (URBR0, URBR1) ...................................................... 12-6

12.3.1.2

Transmitter Holding Registers (UTHR0, UTHR1) ............................................... 12-6

12.3.1.3

Divisor Most and Least Significant Byte Registers

(UDMB and UDLB).......................................................................................... 12-7

12.3.1.4

Interrupt Enable Register (UIER).......................................................................... 12-9

12.3.1.5

Interrupt ID Registers (UIIR0, UIIR1) ................................................................ 12-10

12.3.1.6

FIFO Control Registers (UFCR0, UFCR1) ......................................................... 12-11

12.3.1.7

Line Control Registers (ULCR0, ULCR1).......................................................... 12-12

12.3.1.8

MODEM Control Registers (UMCR0, UMCR1)................................................ 12-14

12.3.1.9

Line Status Registers (ULSR0, ULSR1) ............................................................. 12-15

12.3.1.10

MODEM Status Registers (UMSR0, UMSR1) ................................................... 12-16

12.3.1.11

Scratch Registers (USCR0, USCR1) ................................................................... 12-17

12.3.1.12

Alternate Function Registers (UAFR0, UAFR1) ................................................ 12-17

12.3.1.13

DMA Status Registers (UDSR0, UDSR1) .......................................................... 12-18

12.4

Functional Description................................................................................................. 12-20

12.4.1

Serial Interface ......................................................................................................... 12-20

12.4.1.1

START Bit ........................................................................................................... 12-21

12.4.1.2

Data Transfer ....................................................................................................... 12-21

12.4.1.3

Parity Bit .............................................................................................................. 12-22

12.4.1.4

STOP Bit.............................................................................................................. 12-22

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