MPC8540 datasheet(65/1302 Pages) FREESCALE

65 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

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Tables

Table

Number

Title

Page

Number

6-27

MAS1 Field Descriptions—Descriptor Context and Configuration Control........................ 6-38

6-28

MAS2 Field Descriptions—EPN and Page Attributes ......................................................... 6-39

6-29

MAS3 Field Descriptions–RPN and Access Control ........................................................... 6-40

6-30

MAS4 Field Descriptions—Hardware Replacement Assist Configuration.......................... 6-40

6-31

MAS6—TLB Search Context Register 0.............................................................................. 6-41

6-32

DBCR0 Field Descriptions ................................................................................................... 6-42

6-33

DBCR1 Field Descriptions ................................................................................................... 6-44

6-34

DBCR2 Field Descriptions ................................................................................................... 6-45

6-35

DBSR Field Descriptions...................................................................................................... 6-46

6-36

SPEFSCR Field Descriptions................................................................................................ 6-48

6-37

ACC FIeld Descriptions........................................................................................................ 6-50

6-38

Supervisor-Level PMRs (PMR[5] = 1) ................................................................................. 6-51

6-39

User-Level PMRs (PMR[5] = 0) (Read Only)...................................................................... 6-51

6-40

PMGC0 Field Descriptions ................................................................................................... 6-52

6-41

PMLCa0–PMLCa3 Field Descriptions ................................................................................. 6-53

6-42

PMLCb0–PMLCb3 Field Descriptions ................................................................................ 6-54

6-43

PMC0–PMC3 Field Descriptions ......................................................................................... 6-54

7-1

L2/SRAM Memory-Mapped Registers................................................................................... 7-6

7-2

L2CTL Field Descriptions ...................................................................................................... 7-8

7-3

L2CEWARn Field Descriptions............................................................................................ 7-10

7-4

L2CEWCRn Field Descriptions............................................................................................ 7-11

7-5

L2SRBARn Field Descriptions............................................................................................. 7-12

7-6

L2ERRINJHI Field Description............................................................................................ 7-13

7-7

L2ERRINJLO Field Description .......................................................................................... 7-14

7-8

L2ERRINJCTL Field Descriptions....................................................................................... 7-14

7-9

L2CAPTDATAHI Field Description..................................................................................... 7-15

7-10

L2CAPTDATALO Field Description.................................................................................... 7-16

7-11

L2CAPTECC Field Descriptions .......................................................................................... 7-16

7-12

L2ERRDET Field Descriptions ............................................................................................ 7-16

7-13

L2ERRDIS Field Descriptions.............................................................................................. 7-17

7-14

L2ERRINTEN Field Descriptions ........................................................................................ 7-18

7-15

L2ERRATTR Field Descriptions .......................................................................................... 7-19

7-16

L2ERRADDR Field Description .......................................................................................... 7-20

7-17

L2ERRCTL Field Descriptions ............................................................................................ 7-20

7-18

Fastest Read Timing—Hit in L2 ........................................................................................... 7-22

7-19

PLRU Bit Update Algorithm ................................................................................................ 7-28

7-20

PLRU-Based Victim Selection Mechanism .......................................................................... 7-29

7-21

L2 Cache States..................................................................................................................... 7-30

7-22

State Transitions Due to Core-Initiated Transactions ........................................................... 7-31

7-23

State Transitions Due to System-Initiated Transactions ....................................................... 7-33

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