MPC8540 datasheet(35/1302 Pages) FREESCALE

35 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xxxv

Contents

Paragraph

Number

Title

Page

Number

17.3.3.2.4

Inbound Frame Queue Enqueue Pointer Address Register

(IFQEPAR) .................................................................................................. 17-76

17.3.3.3

RapidIO Doorbell Registers ................................................................................ 17-77

17.3.3.3.1

Doorbell Mode Register (DMR)...................................................................... 17-77

17.3.3.3.2

Doorbell Status Register (DSR) ...................................................................... 17-78

17.3.3.3.3

Doorbell Queue/Dequeue Pointer Address Register (DQDPAR).................... 17-79

17.3.3.3.4

Doorbell Queue Enqueue Pointer Address Register (DQEPAR) .................... 17-80

17.3.3.4

RapidIO Port-Write Registers.............................................................................. 17-81

17.3.3.4.1

Port-Write Mode Register (PWMR)................................................................ 17-81

17.3.3.4.2

Port-Write Status Register (PWSR)................................................................. 17-82

17.3.3.4.3

Port-Write Queue Base Address Register (PWQBAR) ................................... 17-83

17.4

Functional Description................................................................................................. 17-83

17.4.1

RapidIO Transaction, Packet, and Control Symbol Summary ................................ 17-83

17.5

RapidIO Functionality ................................................................................................. 17-89

17.5.1

General Functionality Lists...................................................................................... 17-89

17.5.1.1

8/16 LP-LVDS Layer Functionality Lists............................................................ 17-91

17.5.2

Common Transport Layer Functionality Lists......................................................... 17-98

17.5.3

Logical Layer Functionality Lists.......................................................................... 17-100

17.5.3.1

Logical Layer Source Transaction Support List ................................................ 17-101

17.5.3.2

Logical Layer Extended Functionality .............................................................. 17-101

17.6

RapidIO Errors........................................................................................................... 17-102

17.7

ATMU (Address Translation and Mapping Unit) ...................................................... 17-106

17.7.1

Outbound ATMU Translation ................................................................................ 17-106

17.7.1.1

Outbound ATMU Bypass Mode ........................................................................ 17-107

17.7.1.2

Outbound Special Transactions and Requirements ........................................... 17-107

17.7.2

Inbound ATMU Translation................................................................................... 17-107

17.7.2.1

Inbound ATMU LCSBA1CSR Window............................................................ 17-108

17.7.2.2

Inbound ATMU Bypass Mode........................................................................... 17-108

17.7.2.3

Inbound Special Transactions and Requirements .............................................. 17-108

17.7.2.4

ATMU Boundary Crossing Errors ..................................................................... 17-109

17.8

RapidIO Message Unit............................................................................................... 17-109

17.8.1

Overview................................................................................................................ 17-109

17.8.2

Message Unit Features........................................................................................... 17-110

17.8.3

Message Unit Modes of Operation .........................................................................17-111

17.8.4

RapidIO Messaging Description.............................................................................17-111

17.8.4.1

Data Message Controller ....................................................................................17-111

17.8.4.2

Outbox Controller Operation ..............................................................................17-111

17.8.4.2.1

Direct Mode Operation .................................................................................. 17-112

17.8.4.2.2

Chaining Mode Operation ............................................................................. 17-112

17.8.4.2.3

Switching Between Direct and Chaining Modes........................................... 17-115

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