MPC8540 datasheet(63/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

lxiii

Tables

Table

Number

Title

Page

Number

Tables

Acronyms and Abbreviated Terms................................................................................... lxxxviii

2-1

Target Interface Codes ............................................................................................................ 2-1

2-2

Local Access Windows Example............................................................................................ 2-2

2-3

Format of ATMU Window Definitions ................................................................................... 2-3

2-4

Local Access Register Memory Map...................................................................................... 2-5

2-5

LAWBARn Field Descriptions ............................................................................................... 2-6

2-6

LAWARn Field Descriptions .................................................................................................. 2-6

2-7

Overlapping Local Access Windows ...................................................................................... 2-7

2-8

Local Memory Configuration, Control, and Status Register Summary................................ 2-12

2-9

Memory Map......................................................................................................................... 2-16

3-1

MPC8540 Signal Reference by Functional Block .................................................................. 3-4

3-2

MPC8540 Alphabetical Signal Reference .............................................................................. 3-9

3-3

MPC8540 Reset Configuration Signals ................................................................................ 3-16

3-4

Output Signal States During System Reset........................................................................... 3-17

4-1

Signal Summary ...................................................................................................................... 4-1

4-2

System Control Signals—Detailed Signal Descriptions ......................................................... 4-2

4-3

Clock Signals—Detailed Signal Descriptions ........................................................................ 4-3

4-4

Local Configuration Control Register Map ............................................................................ 4-4

4-5

CCSRBAR Field Descriptions................................................................................................ 4-5

4-6

ALTCBAR Field Descriptions ................................................................................................ 4-6

4-7

ALTCAR Field Descriptions................................................................................................... 4-7

4-8

BPTR Field Descriptions ........................................................................................................ 4-8

4-9

CCB Clock PLL Ratio ..........................................................................................................4-13

4-10

e500 Core Clock PLL Ratios ................................................................................................ 4-13

4-11

Boot ROM Location.............................................................................................................. 4-14

4-12

Host/Agent Configuration..................................................................................................... 4-15

4-13

CPU Boot Configuration....................................................................................................... 4-15

4-14

Boot Sequencer Configuration.............................................................................................. 4-16

4-15

TSEC Width Configuration................................................................................................... 4-17

4-16

TSEC1 Protocol Configuration ............................................................................................. 4-17

4-17

TSEC2 Protocol Configuration ............................................................................................. 4-18

4-18

RapidIO Transmit Clock Source ........................................................................................... 4-18

4-19

RapidIO Device ID ............................................................................................................... 4-19

4-20

PCI-32 Configuration............................................................................................................ 4-19

4-21

PCI I/O Impedance................................................................................................................ 4-19

4-22

PCI Arbiter Configuration .................................................................................................... 4-20

4-23

PCI Debug Configuration .....................................................................................................4-20

4-24

PCI/PCI-X Configuration .....................................................................................................4-20

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