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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 138 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 138 Page - Freescale Semiconductor, Inc |
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138 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 2-20 Freescale Semiconductor Memory Map 0x0_4602 UAFR—ULCR[DLAB] = 1 UART1 alternate function register R/W 0x00 12.3.1.12/12-17 0x0_4603 ULCR—ULCR[DLAB] = x UART1 line control register R/W 0x00 12.3.1.7/12-12 0x0_4604 UMCR—ULCR[DLAB] = x UART1 MODEM control register R/W 0x00 12.3.1.8/12-14 0x0_4605 ULSR—ULCR[DLAB] = x UART1 line status register R 0x60 12.3.1.9/12-15 0x0_4606 UMSR—ULCR[DLAB] = x UART1 MODEM status register R0x00 12.3.1.10/12-16 0x0_4607 USCR—ULCR[DLAB] = x UART1 scratch register R/W 0x00 12.3.1.11/12-17 0x0_4610 UDSR—ULCR[DLAB] = x UART1 DMA status register R0x01 12.3.1.13/12-18 Local Bus Controller Registers 0x0_5000 BR0—Base register 0 R/W 0x0000_nn011 13.3.1.1/13-11 0x0_5008 BR1—Base register 1 0x0000_0000 0x0_5010 BR2—Base register 2 0x0_5018 BR3—Base register 3 0x0_5020 BR4—Base register 4 0x0_5028 BR5—Base register 5 0x0_5030 BR6—Base register 6 0x0_5038 BR7—Base register 7 0x0_5004 OR0—Options register 0 R/W 0x0000_0FF7 13.3.1.2/13-12 0x0_500C OR1—Options register 1 0x0000_0000 0x0_5014 OR2—Options register 2 0x0_501C OR3—Options register 3 0x0_5024 OR4—Options register 4 0x0_502C OR5—Options register 5 0x0_5034 OR6—Options register 6 0x0_503C OR7—Options register 7 0x0_5068 MAR—UPM address register R/W 0x0000_0000 13.3.1.3/13-18 0x0_5070 MAMR—UPMA mode register R/W 0x0000_0000 13.3.1.4/13-19 0x0_5074 MBMR—UPMB mode register R/W 0x0000_0000 13.3.1.4/13-19 0x0_5078 MCMR—UPMC mode register R/W 0x0000_0000 13.3.1.4/13-19 0x0_5084 MRTPR—Memory refresh timer prescaler register R/W 0x0000_0000 13.3.1.5/13-21 0x0_5088 MDR—UPM data register R/W 0x0000_0000 13.3.1.6/13-22 0x0_5094 LSDMR—SDRAM mode register R/W 0x0000_0000 13.3.1.7/13-22 0x0_50A0 LURT—UPM refresh timer R/W 0x0000_0000 13.3.1.8/13-24 Table 2-9. Memory Map (continued) Offset Register Access Reset Section/Page |
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