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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 36 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 36 Page - Freescale Semiconductor, Inc |
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36 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 xxxvi Freescale Semiconductor Contents Paragraph Number Title Page Number 17.8.4.2.4 Descriptor Format.......................................................................................... 17-115 17.8.4.2.5 Outbox Controller Interrupts ......................................................................... 17-116 17.8.4.2.6 Special Error Case Condition ........................................................................ 17-117 17.8.4.3 Inbox Controller Operation................................................................................ 17-117 17.8.4.3.1 Retry Response Conditions ........................................................................... 17-118 17.8.4.3.2 Error Response Conditions ............................................................................ 17-118 17.8.4.3.3 Inbox Controller Interrupts ............................................................................ 17-118 17.8.4.3.4 Data Message Controller Limitations and Restrictions ................................. 17-119 17.8.4.4 Doorbell Message Controller............................................................................. 17-119 17.8.4.4.1 Inbound Doorbell Reception ......................................................................... 17-120 17.8.4.4.2 Doorbell Queue Entry Format ....................................................................... 17-120 17.8.4.4.3 Retry Response Conditions ........................................................................... 17-121 17.8.4.4.4 Error Response Conditions ............................................................................ 17-121 17.8.4.4.5 Doorbell Controller Interrupts ....................................................................... 17-121 17.8.4.5 Port-Write Controller Structure ......................................................................... 17-121 17.9 Initialization and Application Information ................................................................ 17-122 Part IV Global Functions and Debug Chapter 18 Global Utilities 18.1 Overview........................................................................................................................ 18-1 18.2 Global Utilities Features ................................................................................................ 18-1 18.2.1 Power Management and Block Disables ................................................................... 18-1 18.2.2 Accessing Current POR Configuration Settings........................................................ 18-1 18.2.3 General-Purpose I/O .................................................................................................. 18-1 18.2.4 Interrupt and Local Bus Signal Multiplexing ............................................................ 18-2 18.2.5 Clock Control............................................................................................................. 18-2 18.3 External Signal Descriptions ......................................................................................... 18-2 18.3.1 Signals Overview ....................................................................................................... 18-2 18.3.2 Detailed Signal Descriptions ..................................................................................... 18-2 18.4 Memory Map/Register Definition ................................................................................. 18-3 18.4.1 Register Descriptions ................................................................................................. 18-4 18.4.1.1 POR PLL Status Register (PORPLLSR) ............................................................... 18-4 18.4.1.2 POR Boot Mode Status Register (PORBMSR)..................................................... 18-5 18.4.1.3 POR I/O Impedance Status and Control Register (PORIMPSCR) ....................... 18-6 18.4.1.4 POR Device Status Register (PORDEVSR).......................................................... 18-7 18.4.1.5 POR Debug Mode Status Register (PORDBGMSR) ............................................ 18-9 |
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