MPC8540 datasheet(26/1302 Pages) FREESCALE

26 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

xxvi

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

14.5.4.6

AN Expansion Register (ANEX)......................................................................... 14-98

14.5.4.7

AN Next Page Transmit Register (ANNPT)........................................................ 14-98

14.5.4.8

AN Link Partner Ability Next Page Register (ANLPANP) ................................ 14-99

14.5.4.9

Extended Status Register (EXST) ..................................................................... 14-100

14.5.4.10

Jitter Diagnostics Register (JD) ......................................................................... 14-101

14.5.4.11

TBI Control Register (TBICON)....................................................................... 14-102

14.6

Functional Description............................................................................................... 14-103

14.6.1

Connecting to Physical Interfaces.......................................................................... 14-103

14.6.1.1

Media-Independent Interface (MII) ................................................................... 14-104

14.6.1.2

Gigabit Media-Independent Interface (GMII) ................................................... 14-104

14.6.1.3

Reduced Gigabit Media-Independent Interface (RGMII) ................................. 14-105

14.6.1.4

Ten-Bit Interface (TBI)...................................................................................... 14-106

14.6.1.5

Reduced Ten-Bit Interface (RTBI) .................................................................... 14-107

14.6.2

Gigabit Ethernet Channel Operation.......................................................................14-111

14.6.2.1

Initialization Sequence........................................................................................14-111

14.6.2.1.1

Hardware-Controlled Initialization.................................................................14-111

14.6.2.1.2

User Initialization ...........................................................................................14-111

14.6.2.2

Soft Reset and Reconfiguring Procedure........................................................... 14-112

14.6.2.3

Gigabit Ethernet Frame Transmission ............................................................... 14-113

14.6.2.4

Gigabit Ethernet Frame Reception .................................................................... 14-115

14.6.2.5

RMON Support.................................................................................................. 14-116

14.6.2.6

Frame Recognition............................................................................................. 14-116

14.6.2.6.1

Destination Address Recognition .................................................................. 14-116

14.6.2.6.2

Hash Table Algorithm.................................................................................... 14-118

14.6.2.6.3

CRC Computation Examples ........................................................................ 14-118

14.6.2.7

Flow Control...................................................................................................... 14-119

14.6.2.8

Interrupt Handling ............................................................................................. 14-120

14.6.2.8.1

Interrupt Coalescing ...................................................................................... 14-121

14.6.2.8.2

Interrupt Coalescing By Frame Count Threshold.......................................... 14-122

14.6.2.8.3

Interrupt Coalescing By Timer Threshold ..................................................... 14-122

14.6.2.9

Inter-Packet Gap Time ....................................................................................... 14-123

14.6.2.10

Internal and External Loop Back ....................................................................... 14-123

14.6.2.11

Error-Handling Procedure.................................................................................. 14-123

14.6.3

Buffer Descriptors.................................................................................................. 14-125

14.6.3.1

Transmit Data Buffer Descriptor (TxBD).......................................................... 14-126

14.6.3.2

Receive Buffer Descriptor (RxBD) ................................................................... 14-128

14.6.4

Data Extraction to the L2 Cache............................................................................ 14-130

14.7

Initialization/Application Information ....................................................................... 14-131

14.7.1

Interface Mode Configuration ............................................................................... 14-131

14.7.1.1

MII Interface Mode............................................................................................ 14-131

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