MPC8540 datasheet(66/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

lxvi

Freescale Semiconductor

Tables

Table

Number

Title

Page

Number

8-1

ECM Memory Map ................................................................................................................. 8-3

8-2

EEBACR Field Descriptions .................................................................................................. 8-3

8-3

EEBPCR Field Descriptions ................................................................................................... 8-4

8-4

EEDR Field Descriptions........................................................................................................ 8-6

8-5

EEER Field Descriptions ........................................................................................................ 8-7

8-6

EEATR Field Descriptions...................................................................................................... 8-7

8-7

EEADR Field Descriptions .....................................................................................................8-8

9-1

DDR Memory Interface Signal Summary .............................................................................. 9-4

9-2

Memory Address Signal Mappings......................................................................................... 9-4

9-3

Memory Interface Signals—Detailed Signal Descriptions ..................................................... 9-5

9-4

Clock Signals—Detailed Signal Descriptions ........................................................................ 9-8

9-5

DDR Memory Controller Memory Map ................................................................................. 9-9

9-6

CSn_BNDS Field Descriptions............................................................................................. 9-10

9-7

CSn_CONFIG Field Descriptions ........................................................................................ 9-11

9-8

TIMING_CFG_1 Field Descriptions .................................................................................... 9-12

9-9

TIMING_CFG_2 Register Field Descriptions...................................................................... 9-13

9-10

DDR_SDRAM_CFG Field Descriptions.............................................................................. 9-15

9-11

DDR_SDRAM_MODE Field Descriptions.......................................................................... 9-16

9-12

DDR_SDRAM_INTERVAL Field Descriptions .................................................................. 9-17

9-13

DATA_ERR_INJECT_HI Field Descriptions....................................................................... 9-17

9-14

DATA_ERR_INJECT_LO Field Descriptions ..................................................................... 9-18

9-15

ECC_ERR_INJECT Field Descriptions ............................................................................... 9-19

9-16

CAPTURE_DATA_HI Field Descriptions............................................................................ 9-19

9-17

CAPTURE_DATA_LO Field Descriptions........................................................................... 9-20

9-18

CAPTURE_ECC Field Descriptions .................................................................................... 9-20

9-19

ERR_DETECT Field Descriptions ....................................................................................... 9-21

9-20

ERR_DISABLE Field Descriptions...................................................................................... 9-22

9-21

ERR_INT_EN Field Descriptions ........................................................................................ 9-23

9-22

CAPTURE_ATTRIBUTES Field Descriptions .................................................................... 9-23

9-23

CAPTURE_ADDRESS Field Descriptions .......................................................................... 9-24

9-24

ERR_SBE Field Descriptions ............................................................................................... 9-25

9-25

Byte Lane to Data Relationship ............................................................................................ 9-30

9-26

Supported DDR SDRAM Device Configurations ................................................................ 9-31

9-27

DDR SDRAM Address Multiplexing ................................................................................... 9-32

9-28

SDRAM Command Table ..................................................................................................... 9-34

9-29

DDR SDRAM Interface Timing Intervals ............................................................................ 9-35

9-30

DDR SDRAM Power-Saving Modes Refresh Configuration............................................... 9-43

9-31

Memory Controller–Data Beat Ordering .............................................................................. 9-45

9-32

DDR SDRAM ECC Syndrome Encoding ............................................................................ 9-46

9-33

DDR SDRAM ECC Syndrome Encoding (Check Bits) ....................................................... 9-48

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