MPC8540 datasheet(27/1302 Pages) FREESCALE

27 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xxvii

Contents

Paragraph

Number

Title

Page

Number

14.7.1.2

GMII Interface Mode......................................................................................... 14-135

14.7.1.3

TBI Interface Mode ........................................................................................... 14-138

14.7.1.4

RGMII Interface Mode ...................................................................................... 14-143

14.7.1.5

RTBI Interface Mode ......................................................................................... 14-147

Chapter 15

DMA Controller

15.1

Introduction.................................................................................................................... 15-1

15.1.1

Block Diagram........................................................................................................... 15-1

15.1.2

Overview.................................................................................................................... 15-1

15.1.3

Features ...................................................................................................................... 15-2

15.1.4

Modes of Operation ................................................................................................... 15-2

15.2

External Signal Descriptions ......................................................................................... 15-5

15.2.1

Signal Overview ........................................................................................................ 15-5

15.2.2

Detailed Signal Descriptions ..................................................................................... 15-6

15.3

Memory Map/Register Definition ................................................................................. 15-6

15.3.1

Module Memory Map................................................................................................ 15-7

15.3.2

DMA Register Descriptions..................................................................................... 15-10

15.3.2.1

Mode Registers (MRn) ........................................................................................ 15-10

15.3.2.2

Status Registers (SRn) ......................................................................................... 15-13

15.3.2.3

Current Link Descriptor Address Registers (CLNDARn)................................... 15-14

15.3.2.4

Source Attributes Registers (SATRn).................................................................. 15-16

15.3.2.5

Source Address Registers (SARn)....................................................................... 15-18

15.3.2.5.1

Source Address Registers for RapidIO Maintenance Reads

(SARn)......................................................................................................... 15-19

15.3.2.6

Destination Attributes Registers (DATRn).......................................................... 15-19

15.3.2.7

Destination Address Registers (DARn)............................................................... 15-21

15.3.2.7.1

Destination Address Registers for RapidIO Maintenance Writes

(DARn) ........................................................................................................ 15-22

15.3.2.8

Byte Count Registers (BCRn) ............................................................................. 15-23

15.3.2.9

Next Link Descriptor Address Registers (NLNDARn)....................................... 15-23

15.3.2.10

Current List Descriptor Address Registers (CLSDARn)..................................... 15-24

15.3.2.11

Next List Descriptor Address Registers (NLSDARn)......................................... 15-25

15.3.2.12

Source Stride Registers (SSRn) ........................................................................... 15-25

15.3.2.13

Destination Stride Registers (DSRn) ................................................................... 15-26

15.3.2.14

DMA General Status Register (DGSR) ............................................................... 15-26

15.4

Functional Description................................................................................................. 15-28

15.4.1

DMA Channel Operation......................................................................................... 15-28

15.4.1.1

Basic DMA Mode Transfer ................................................................................. 15-29

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