MPC8540 datasheet(98/1302 Pages) FREESCALE

98 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

1-4

Freescale Semiconductor

Overview

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DDR memory controller

— Programmable timing supporting DDR-1 SDRAM

— 64-bit data interface, up to 333-MHz data rate

— Four banks of memory supported, each up to 1 Gbyte

— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports

— Full ECC support

— Page mode support (up to 16 simultaneous open pages)

— Contiguous or discontiguous memory mapping

— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear

transactions

— Sleep mode support for self-refresh SDRAM

— Supports auto refreshing

— On-the-fly power management using CKE signal

— Registered DIMM support

— Fast memory access through JTAG port

— 2.5-V SSTL2 compatible I/O

•

RapidIO interface unit

— 8-bit RapidIO I/O and messaging protocols

— Source-synchronous double data rate (DDR) interfaces

— Supports small type systems (small domain, 8-bit device ID)

— Supports four priority levels (ordering within a level)

— Reordering across priority levels

— Maximum data payload of 256 bytes per packet

— Packet pacing support at the physical layer

— CRC protection for packets

— Supports atomic operations increment, decrement, set, and clear

— LVDS signaling

•

RapidIO compliant message unit

— One inbound data message structure (inbox)

— One outbound data message structure (outbox)

— Supports chaining and direct modes in the outbox

— Support of up to 16 packets per message

— Support of up to 256 bytes per packet and up to 4 Kbytes of data per message

— Supports one inbound doorbell message structure

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