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MPC8540 датащи(PDF) 75 Page - Freescale Semiconductor, Inc

номер детали MPC8540
подробное описание детали  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 датащи(HTML) 75 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
lxxv
Tables
Table
Number
Title
Page
Number
16-37
64-Bit Low Memory Base Address Register Field Descriptions........................................ 16-45
16-38
64-Bit High Memory Base Address Register Field Description......................................... 16-46
16-39
PCI Subsystem Vendor ID Register Field Description ....................................................... 16-46
16-40
PCI Subsystem ID Register Field Description.................................................................... 16-47
16-41
PCI Bus Capabilities Pointer Register Field Description ................................................... 16-47
16-42
PCI Bus Interrupt Line Register Field Description............................................................. 16-48
16-43
PCI Bus Interrupt Pin Register Field Description............................................................... 16-48
16-44
PCI Bus Minimum Grant Register Field Description ......................................................... 16-48
16-45
PCI Bus Maximum Latency Register Field Description .................................................... 16-49
16-46
PCI Bus Function Register Field Descriptions ................................................................... 16-49
16-47
PCI Bus Arbiter Configuration Register Field Descriptions .............................................. 16-50
16-48
PCI-X Next Capabilities ID Register Field Descriptions ................................................... 16-51
16-49
PCI-X Capability Pointer Register Field Description......................................................... 16-52
16-50
PCI-X Command Register Field Descriptions.................................................................... 16-52
16-51
PCI-X Status Register Field Descriptions........................................................................... 16-53
16-52
PCI Bus Commands ............................................................................................................ 16-58
16-53
Supported Combinations of PCI_AD[1:0].......................................................................... 16-59
16-54
PCI Configuration Space Header Summary ....................................................................... 16-72
16-55
PCI Type 0 Configuration—Device Number to ADn Translation...................................... 16-75
16-56
Special-Cycle Message Encodings ..................................................................................... 16-77
16-57
PCI Mode Error Actions ..................................................................................................... 16-80
16-58
PCI-X Command Encodings............................................................................................... 16-82
16-59
Burst/DWORD Transaction Attribute Summary ................................................................ 16-84
16-60
Split Completion Transaction Address ............................................................................... 16-91
16-61
PCI-X Split Completion Transaction Attribute Summary .................................................. 16-92
16-62
PCI-X Split Completion Message Summary ...................................................................... 16-93
16-63
PCI-X Type 0 Configuration—Device Number to ADn Translation ................................. 16-95
16-64
PCI-X Configuration Transaction Attribute Summary ....................................................... 16-96
16-65
PCI-X Mode Error Actions ................................................................................................. 16-97
16-66
Affected Configuration Register Bits for POR ................................................................... 16-99
16-67
Power-On Reset Values for Affected Configuration Bits ................................................. 16-100
17-1
RapidIO Terminology ........................................................................................................... 17-4
17-2
CRC Checking Mode ............................................................................................................ 17-6
17-3
Accept All Mode Behavior ................................................................................................... 17-6
17-4
RapidIO Interface Signals Summary .................................................................................... 17-7
17-5
RapidIO Interface Signals—Detailed Signal Descriptions ................................................... 17-8
17-6
RapidIO Module Memory Map ............................................................................................ 17-9
17-7
DIDCAR Field Descriptions ............................................................................................... 17-13
17-8
DICAR Field Description ................................................................................................... 17-14
17-9
AIDCAR Field Descriptions ............................................................................................... 17-14



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