MPC8540 datasheet(136/1302 Pages) FREESCALE

136 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

2-18

Freescale Semiconductor

Memory Map

0x0_2080

CS0_CONFIG—Chip select 0 configuration

R/W

0x0000_0000

9.4.1.2/9-10

0x0_2084

CS1_CONFIG—Chip select 1 configuration

0x0_2088

CS2_CONFIG—Chip select 2 configuration

0x0_208C

CS3_CONFIG—Chip select 3 configuration

0x0_2108

TIMING_CFG_1—DDR SDRAM timing configuration

R/W

0x0000_0000

9.4.1.3/9-11

0x0_210C

TIMING_CFG_2—DDR SDRAM timing configuration

R/W

0x0000_0000

9.4.1.4/9-13

0x0_2110

DDR_SDRAM_CFG—DDR SDRAM control

configuration

R/W

0x0200_0000

9.4.1.5/9-14

0x0_2118

DDR_SDRAM_MODE—DDR SDRAM mode

configuration

R/W

0x0000_0000

9.4.1.6/9-16

0x0_2124

DDR_SDRAM_INTERVAL—DDR SDRAM interval

configuration

R/W

0x0000_0000

9.4.1.7/9-16

0x0_2E00

DATA_ERR_INJECT_HI—Memory data path error

injection mask high

R/W

0x0000_0000

9.4.1.8/9-17

0x0_2E04

DATA_ERR_INJECT_LO—Memory data path error

injection mask low

R/W

0x0000_0000

9.4.1.9/9-18

0x0_2E08

ECC_ERR_INJECT—Memory data path error

injection mask ECC

R/W

0x0000_0000

9.4.1.10/9-18

0x0_2E20

CAPTURE_DATA_HI—Memory data path read

capture high

R/W

0x0000_0000

9.4.1.11/9-19

0x0_2E24

CAPTURE_DATA_LO—Memory data path read

capture low

R/W

0x0000_0000

9.4.1.12/9-20

0x0_2E28

CAPTURE_ECC—Memory data path read capture

ECC

R/W

0x0000_0000

9.4.1.13/9-20

0x0_2E40

ERR_DETECT—Memory error detect

R/W

0x0000_0000

9.4.1.14/9-21

0x0_2E44

ERR_DISABLE—Memory error disable

R/W

0x0000_0000

9.4.1.15/9-21

0x0_2E48

ERR_INT_EN—Memory error interrupt enable

R/W

0x0000_0000

9.4.1.16/9-22

0x0_2E4C

CAPTURE_ATTRIBUTES—Memory error attributes

capture

R/W

0x0000_0000

9.4.1.17/9-23

0x0_2E50

CAPTURE_ADDRESS—Memory error address

capture

R/W

0x0000_0000

9.4.1.18/9-24

0x0_2E58

ERR_SBE—Single-Bit ECC memory error

management

R/W

0x0000_0000

9.4.1.19/9-25

I2C

0x0_3000

I2CADR—I2C address register

R/W

0x00

11.3.1.1/11-5

0x0_3004

I2CFDR—I2C frequency divider register

R/W

0x00

11.3.1.2/11-5

0x0_3008

I2CCR—I2C control register

R/W

0x00

11.3.1.3/11-6

0x0_300C

I2CSR—I2C status register

R/W

0x81

11.3.1.4/11-7

Table 2-9. Memory Map (continued)

Offset

Access

Reset

Section/Page

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