MPC8540 datasheet(135/1302 Pages) FREESCALE

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Complete CCSR Map

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

2-17

Local-Access Registers—Local-Access Window Base and Size Registers

0x0_0C08

LAWBAR0—Local access window 0 base address

R/W

0x0000_0000

2.2.3.2/2-6

0x0_0C10

LAWAR0—Local access window 0 attribute register

R/W

0x0000_0000

2.2.3.3/2-6

0x0_0C28

LAWBAR1—Local access window 1 base address

R/W

0x0000_0000

2.2.3.2/2-6

0x0_0C30

LAWAR1—Local access window 1 attribute register

R/W

0x0000_0000

2.2.3.3/2-6

0x0_0C48

LAWBAR2—Local access window 2 base address

R/W

0x0000_0000

2.2.3.2/2-6

0x0_0C50

LAWAR2—Local access window 2 attribute register

R/W

0x0000_0000

2.2.3.3/2-6

0x0_0C68

LAWBAR3—Local access window 3 base address

R/W

0x0000_0000

2.2.3.2/2-6

0x0_0C70

LAWAR3—Local access window 3 attribute register

R/W

0x0000_0000

2.2.3.3/2-6

0x0_0C88

LAWBAR4—Local access window 4 base address

R/W

0x0000_0000

2.2.3.2/2-6

0x0_0C90

LAWAR4—Local access window 4 attribute register

R/W

0x0000_0000

2.2.3.3/2-6

0x0_0CA8

LAWBAR5—Local access window 5 base address

R/W

0x0000_0000

2.2.3.2/2-6

0x0_0CB0

LAWAR5—Local access window 5 attribute register

R/W

0x0000_0000

2.2.3.3/2-6

0x0_0CC8

LAWBAR6—Local access window 6 base address

R/W

0x0000_0000

2.2.3.2/2-6

0x0_0CD0

LAWAR6—Local access window 6 attribute register

R/W

0x0000_0000

2.2.3.3/2-6

0x0_0CE8

LAWBAR7—Local access window 7 base address

R/W

0x0000_0000

2.2.3.2/2-6

0x0_0CF0

LAWAR7—Local access window 7 attribute register

R/W

0x0000_0000

2.2.3.3/2-6

Registers

0x0_1000

EEBACR—ECM CCB address configuration register

R/W

0x0000_0003

8.2.1.1/8-3

0x0_1010

EEBPCR—ECM CCB port configuration register

R/W

0x0n00_0000

8.2.1.2/8-4

0x0_1E00

EEDR—ECM error detect register

R/W

0x0000_0000

8.2.1.3/8-5

0x0_1E08

EEER—ECM error enable register

R/W

0x0000_0000

8.2.1.4/8-6

0x0_1E0C

EEATR—ECM error attributes capture register

0x0000_0000

8.2.1.5/8-7

0x0_1E10

EEADR—ECM error address capture register

0x0000_0000

8.2.1.6/8-8

DDR Memory Controller Memory Map

0x0_2000

CS0_BNDS—Chip select 0 memory bounds

R/W

0x0000_0000

9.4.1.1/9-10

0x0_2008

CS1_BNDS—Chip select 1 memory bounds

0x0_2010

CS2_BNDS—Chip select 2 memory bounds

0x0_2018

CS3_BNDS—Chip select 3 memory bounds

Table 2-9. Memory Map (continued)

Offset

Access

Reset

Section/Page

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