MPC8540 datasheet(110/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

1-16

Freescale Semiconductor

Overview

The I

2C controller is a true multiple-master bus; it includes collision detection and arbitration that

prevents data corruption if two or more masters attempt to control the bus simultaneously. This

feature allows for complex applications with multiprocessor control. The I

2C controller consists

of a transmitter/receiver unit, a clocking unit, and a control unit. The I

2C unit supports general

broadcast mode, and on-chip filtering rejects spikes on the bus.

1.3.7

Boot Sequencer

The MPC8540 provides a boot sequencer that uses the I

2C interface to access an external serial

ROM and loads the data into the MPC8540’s configuration registers. The boot sequencer is

enabled by a configuration pin sampled at the negation of the MPC8540 hardware reset signal. If

enabled, the boot sequencer holds the MPC8540 processor core in reset until the boot sequence is

complete. If the boot sequencer is not enabled, the processor core exits reset and fetches boot code

in default configurations.

1.3.8

Dual Universal Asynchronous Receiver/Transmitter

(DUART)

The MPC8540 includes a DUART intended for use in maintenance, bringing-up, and debugging

of systems. The MPC8540 provides a standard four-wire handshake (SIN, SOUT, RTS, CTS) for

each port. The DUART is a slave interface. An interrupt is provided to the interrupt controller or

optionally steered externally to allow device handshakes. Interrupts are generated for transmit,

receive, line status, and MODEM status.

The MPC8540 DUART supports full-duplex operation. It is compatible with the PC16450 and

PC16550 programming models. Also, 16-byte FIFOs are supported for both the transmitter and

the receiver.

Software programmable baud generators divide the system clock to generate a 16x clock. Serial

interface data formats (data length, parity, 1/1.5/2 STOP bit, baud rate) are also software

selectable.

1.3.9

10/100 Fast Ethernet Controller

The MPC8540 provides a 10/100 fast Ethernet controller operating at 10 to 100 Mbps as a device

debug and maintenance port. The gigabit three-speed Ethernet controllers (TSECs) are separate

from this 10/100 fast Ethernet controller and are defined and described in Chapter 14,

“Three-Speed Ethernet Controllers.”

The 10/100 Ethernet standard supports the IEEE 802.3 Ethernet frame format, backward

compatibility for installed media, and the use of full- or half-duplex CSMA/CD. The Ethernet

protocol implements the bottom two layers of the open systems interconnection (OSI) 7-layer

model, that is, the data-link and physical sublayers.

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