MPC8540 datasheet(112/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

1-18

Freescale Semiconductor

Overview

1.3.12 Integrated DMA

The MPC8540 DMA engine is capable of transferring blocks of data from any legal address range

to any other legal address range. Therefore, it can perform a DMA transfer between any of its I/O

or memory ports or even between two devices or locations on the same port.

The four-channel DMA controller allows chaining (both extended and direct) through local

memory-mapped chain descriptors. Scattering, gathering, and misaligned transfers are supported.

In addition, advanced capabilities such as stride transfers and complex transaction chaining are

supported.

DMA transfers can be initiated by a single write to a configuration register. There is also support

for external control of transfers using DMA_DREQ, DMA_DACK, and DMA_DDONE

handshake signals.

DMA descriptors encompass a rich set of attributes that allow DMA transfers to bypass outbound

address translation and supply external addresses and attributes directly to the RapidIO port. Local

attributes such as snoop and L2-write stashing can be specified by descriptors.

Interrupts are provided on a completed segment, link, list, chain, or on an error condition.

Coherency is selectable and hardware enforced (snoop/no snoop).

1.3.13 PCI Controller

The MPC8540 64-bit PCI controller is compatible with the PCI Local Bus Specification, Revision

2.2 and the PCI-X Addendum, Revision 1.0. The interface can function as a host or agent bridge

interface in either PCI or PCI-X mode. Both PCI and PCI-X modes support 64-bit addressing and

32-bit or 64-bit data buses.

As a master, the MPC8540 supports read and write operations to the PCI memory space, the PCI

I/O space, and the PCI configuration space. Also, the MPC8540 can generate PCI special-cycle

and interrupt-acknowledge commands. As a target, the MPC8540 supports read and write

operations to system memory as well as configuration accesses.

PCI-X functionality includes split transaction support for four outstanding split transactions. Split

response data is returned in order without interleaving. As a target, the MPC8540 supports all

PCI-X sizes. As a master it internally combines transactions up to 256 bytes.

An internal arbiter can be used to support up to five external masters. A round robin arbitration

algorithm with two priority levels is used.

1.3.14 RapidIO Controller

The RapidIO interconnect unit on the MPC8540 is based on the RapidIO Interconnect

Specification, Revision 1.1. RapidIO is a high-performance, point-to-point, low-pin-count,

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